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    Providing a memory device having a shared error feedback pin
    1.
    发明授权
    Providing a memory device having a shared error feedback pin 有权
    提供具有共享错误反馈引脚的存储器件

    公开(公告)号：US08359521B2

    公开(公告)日：2013-01-22

    申请号：US12018030

    申请日：2008-01-22

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    IPC分类号： H03M13/00 ,  G11C29/00

    CPC分类号： G06F11/1004

    摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

    摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

    SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN
    2.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN 有权
    用于提供具有共享错误反馈PIN的存储器件的系统和方法

    公开(公告)号：US20090187794A1

    公开(公告)日：2009-07-23

    申请号：US12018030

    申请日：2008-01-22

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1004

    摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

    摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

    MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING
    6.
    发明申请
    MEMORY SYSTEM WITH DYNAMIC SUPPLY VOLTAGE SCALING 审中-公开
    具有动态电压范围的存储器系统

    公开(公告)号：US20100138684A1

    公开(公告)日：2010-06-03

    申请号：US12326126

    申请日：2008-12-02

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Alan Gara ,  Vipin Patel ,  Kenneth L. Wright

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Alan Gara ,  Vipin Patel ,  Kenneth L. Wright

    IPC分类号： G06F1/04 ,  G06F1/08

    CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

    摘要： A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.

    摘要翻译： 提供了一种存储器控制器，存储器件和用于存储器系统中的动态电源电压缩放的方法。 该方法包括在存储器系统中的存储器控​​制器处接收对电源电压变化的请求，为存储器件提供电源电压。 该方法还包括等待存储器设备的任何当前访问以完成存储器控制器和存储器设备之间的时钟的禁用。 该方法还包括响应于该请求改变电源电压，并启用时钟。

    SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES
    8.
    发明申请
    SYSTEM FOR PROVIDING READ CLOCK SHARING BETWEEN MEMORY DEVICES 失效
    用于在存储器件之间提供读取时钟共享的系统

    公开(公告)号：US20090161475A1

    公开(公告)日：2009-06-25

    申请号：US11959711

    申请日：2007-12-19

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： G11C8/18

    CPC分类号： G11C5/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03L7/07 ,  H03L7/0812

    摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.

    摘要翻译： 一种用于在存储器件之间提供读时钟共享的系统。 该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。 相位比较器同步存储器件产生的内部读时钟。 相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。 利用同步的结果刷新内部读时钟。 存储器件还包括机构，读时钟驱动器和模式寄存器配合。 该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。 读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。 模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

    SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM
    9.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
    用于在存储器系统中提供错误校正和检测的系统和方法

    公开(公告)号：US20090049365A1

    公开(公告)日：2009-02-19

    申请号：US11837785

    申请日：2007-08-13

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Luis A. Lastras-Montano

    IPC分类号： G11C29/00 ,  G06F11/16

    CPC分类号： G06F11/1012 ,  G11C2029/0411

    摘要： A system and method for providing error correction and detection in a memory system. The memory system includes a plurality of memory devices, and error detection and correction logic. The error detection and correction logic includes instructions for generating an error correction code (ECC) word that includes bits from two more of the memory devices and from different memory device transfers.

    摘要翻译： 一种用于在存储器系统中提供纠错和检测的系统和方法。 存储器系统包括多个存储器件，以及错误检测和校正逻辑。 错误检测和校正逻辑包括用于生成包括来自两个以上存储器设备的位和来自不同存储器件传输的位的纠错码（ECC）字的指令。

    Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel
    10.
    发明授权
    Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel 有权
    实现并行访问的多个存储器设备的时序校准和同步存储器活动

    公开(公告)号：US08909878B2

    公开(公告)日：2014-12-09

    申请号：US13494280

    申请日：2012-06-12

    申请人： Paul W. Coteus ,  Kyu-hyoun Kim

    发明人： Paul W. Coteus ,  Kyu-hyoun Kim

    IPC分类号： G06F12/00

    CPC分类号： G11C29/26 ,  G06F13/1684 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/2602

    摘要： A method and circuit for implementing synchronized memory activities of multiple memory devices being accessed in parallel, and a design structure on which the subject circuit resides are provided. Each memory circuit generates an internal status signal for predefined internal memory activities and provides an output signal coupled to the multiple memory devices. Each memory circuit monitors the generated internal status signal and the output signal of at least one of the multiple memory devices, and responsive to the monitored signals generates a control signal for adjusting operation of its memory activities to synchronize memory activities of the memory devices.

    摘要翻译： 一种用于实现并行访问的多个存储器件的同步存储器活动的方法和电路，以及设置有被摄体电路的设计结构。 每个存储器电路产生用于预定义的内部存储器活动的内部状态信号，并提供耦合到多个存储器件的输出信号。 每个存储器电路监视生成的内部状态信号和多个存储器件中的至少一个的输出信号，并且响应于所监视的信号产生用于调整其存储器活动的操作以控制存储器件的存储器活动的控制信号。