Camouflaged circuit structure with step implants
    31.
    发明授权
    Camouflaged circuit structure with step implants 失效
    具有步进式植入物的伪装电路结构

    公开(公告)号:US5973375A

    公开(公告)日:1999-10-26

    申请号:US869524

    申请日:1997-06-06

    IPC分类号: H01L21/74 H01L27/02 H01L29/78

    摘要: Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.

    摘要翻译: 半导体衬底中的注入区域(例如相邻晶体管的源极或漏极)之间的连接通过掩埋导电植入而不是上层金属化而制成。 当需要连接时,通过注入与注入区相同的掺杂电导率的导电掩埋层和当不需要连接时与注入区相反的导电性的场注入来伪装两个注入区之间的连接的存在或不存在 ,并且在掩模层或场注入的边界处,在通过反向工程师进行选择性蚀刻期间掩蔽形成在不同导电区域之间的步骤的步骤,形成步骤。 掩蔽步骤优选由终止于掩埋层和场植入物的边界的场氧化物层形成。

    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
    32.
    发明授权
    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效
    使用模糊特征对集成电路中的有源区域进行可编程连接和隔离,从而使反向工程师混淆

    公开(公告)号:US08168487B2

    公开(公告)日:2012-05-01

    申请号:US11855005

    申请日:2007-09-13

    IPC分类号: H01L21/335

    摘要: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

    摘要翻译: 用于伪装集成电路结构的技术和结构,并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管,至少一些晶体管是具有侧壁间隔物的类型,其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接,这些不明确的互连特征各自包括形成在半导体衬底中的通道,其优选地与LDD区域具有相同的掺杂剂密度,其中选定的通道由导电类型形成,支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成,但是对于逆向工程师而言,这些通道似乎是支持电气通信。

    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
    38.
    发明授权
    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效
    使用模糊特征对集成电路中的有源区域进行可编程连接和隔离,从而使反向工程师混淆

    公开(公告)号:US08564073B1

    公开(公告)日:2013-10-22

    申请号:US13423155

    申请日:2012-03-16

    IPC分类号: H01L29/66

    摘要: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

    摘要翻译: 用于伪装集成电路结构的技术和结构,并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管,至少一些晶体管是具有侧壁间隔物的类型,其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接,这些不明确的互连特征各自包括形成在半导体衬底中的通道,其优选地与LDD区域具有相同的掺杂剂密度,其中选定的通道由导电类型形成,支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成,但是对于逆向工程师而言,这些通道似乎是支持电气通信。

    Ion evaporation source for tin
    40.
    发明授权
    Ion evaporation source for tin 失效
    锡离子蒸发源

    公开(公告)号:US5006715A

    公开(公告)日:1991-04-09

    申请号:US352440

    申请日:1989-05-16

    IPC分类号: H01J27/26

    CPC分类号: H01J27/26

    摘要: An ion evaporation source for tin ions is prepared by coating a source element with a wettability enhancing gallium coating, and then loading the source with tin. The tin may be the naturally occurring tin, but can be an enriched tin containing a higher concentration of Sn.sup.120. The source produces a beam having a high fraction of Sn.sup.+ and Sn.sup.++ ions, and a small amount of the ionized wettability coating material. All but the desired ions are readily separated from the beam.

    摘要翻译: 通过涂覆具有润湿性增强镓涂层的源元件,然后用锡负载源来制备用于锡离子的离子蒸发源。 锡可以是天然存在的锡,但可以是含有较高浓度Sn120的富集锡。 该源产生具有高分数的Sn +和Sn ++离子的束,以及少量的电离润湿性涂层材料。 除了所需的离子之外,所有离子都容易与光束分离。