公开(公告)号：US5622879A

公开(公告)日：1997-04-22

申请号：US456143

申请日：1995-05-31

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  H01L29/42324

Abstract: The invention relates to a novel electrically programmable and erasable memory cell.The cell comprises a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain (12) and the floating gate (18). The capacitive coupling between the source (10) and the floating gate is low, as is normally the case. Preferably, the control gate (22) only partly covers the floating gate (18). Another part of the floating gate is covered by a semiconductor layer (26) connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.

Abstract translation: 本发明涉及一种新型的电可编程和可擦除存储单元。 该单元包括单晶体管，其为浮栅晶体管，并且不具有选择晶体管。 提供了用于在漏极（12）和浮动栅极（18）之间建立高电容耦合的装置。 源极（10）和浮动栅极之间的电容耦合是低的，正如通常情况。 优选地，控制栅极（22）仅部分地覆盖浮动栅极（18）。 浮置栅极的另一部分由连接到漏极的半导体层（26）覆盖。 建立根据本发明的高电容耦合的后一层。 然后可以通过Fowler-Nordheim效应在高阻抗下进行编程，即没有热电子效应。

公开(公告)号：US5099451A

公开(公告)日：1992-03-24

申请号：US272123

申请日：1988-11-16

Applicant: Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

Inventor： Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/005 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/06 ,  G11C16/10

Abstract: To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.

Abstract translation: 为了避免差异化，在制造中，在相同存储器阵列的随机存取存储器单元和只读存储器单元之间，存储单元都由相同的技术制成。 这些存储单元基本上采用浮置晶体管。 随机存取存储器单元以静态方式通过在晶体管的浮置栅极中注入或不注入电子来编程。 只读存储器单元通过选择性地注入杂质而不是在这些存储单元的浮置栅晶体管的导通通道中被置于编程状态或未编程状态。 改进了对这些存储器单元的隐藏内容的改进的隐藏，同时提高了制作原型的条件。

公开(公告)号：US4860256A

公开(公告)日：1989-08-22

申请号：US133626

申请日：1987-12-16

Applicant: Jean Devin ,  Philippe Calzi

Inventor： Jean Devin ,  Philippe Calzi

IPC: G11C11/401 ,  G11C5/14 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/785 ,  G11C17/18 ,  G11C5/14

Abstract: In an integrated circuit provided with a memory including redundancy elements and fuses for switching-over to the redundancy elements, a supplementary terminal for receiving a high voltage is connected to all the fuses and to a circuit which generates low voltage at the time of programming of the memory and which is capable of presenting high impedance when the high voltage is applied, with the result that the entire current flows through the fuses selected for blowout.

Abstract translation: 在具有包括用于切换到冗余元件的冗余元件和熔丝的存储器的集成电路中，用于接收高电压的辅助端子连接到所有保险丝和编程时产生低电压的电路 存储器，并且当施加高电压时能够呈现高阻抗，结果是整个电流流过选择用于喷射的保险丝。

公开(公告)号：US20070201278A1

公开(公告)日：2007-08-30

申请号：US11742334

申请日：2007-04-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US07218553B2

公开(公告)日：2007-05-15

申请号：US11215311

申请日：2005-08-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US20060056239A1

公开(公告)日：2006-03-16

申请号：US11215311

申请日：2005-08-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US6141254A

公开(公告)日：2000-10-31

申请号：US355064

申请日：1999-11-26

Applicant: Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

Inventor： Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/00

CPC classification number: G11C16/12 ,  G11C16/10

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract translation: PCT No.PCT / FR98 / 00111 Sec。 一九九九年十一月二十二日 102（e）日期1999年11月26日PCT提交1998年1月22日PCT公布。 出版物WO98 / 33187 日期：1998年7月30日本发明涉及一种用于编程闪存EPROM型存储器（1）的方法，该存储器包括排列成行（23）和列（31）的存储单元的字，其中浮栅晶体管（7） 作为存储装置，同一字（10）中的存储单元（2-9）的浮栅晶体管的控制栅极连接到相同的字线连接（30），并且其源极连接到相同的主电极 选择晶体管（26）的另一主电极（28）连接到垂直字源连接（25），其中M个存储单元（2,2b）以N个不同字（10 ，200），其中M小于一个字中的存储器单元的数量P，并且其中M，N和P是整数。

公开(公告)号：US06060932A

公开(公告)日：2000-05-09

申请号：US118953

申请日：1998-07-17

Applicant: Jean Devin

Inventor： Jean Devin

IPC: H02M3/07 ,  G06F1/04

CPC classification number: H02M3/07

Abstract: In integrated circuits, to modify the operation of the charge pumps or voltage step-up circuits, they are sent a variable frequency signal at the input with the aim of breaking the regularity of the pulse train that enters the charge pump. This limits the risks of entry into resonance and limits radiation at a given frequency. The variable frequency signal is typically produced by a logic circuit and by a main oscillator whose transmission of certain pulses is masked by the combined action of different masking signals. The duty cycle ratios of the masking signals are less than that of the signal from the main oscillator. Such duty cycle ratios are preferably produced following the passage of a signal to a lower frequency than that of the signal of the main oscillator in a circuit for the detection of high transitions.

Abstract translation: 在集成电路中，为了修改电荷泵或升压电路的运行，它们在输入端发送可变频率信号，目的是破坏进入电荷泵的脉冲序列的规律性。 这限制了进入共振的风险，并限制了给定频率的辐射。 可变频率信号通常由逻辑电路和主振荡器产生，其中某些脉冲的传输被不同屏蔽信号的组合作用所掩蔽。 屏蔽信号的占空比比小于来自主振荡器的信号的占空比。 优选地，在用于检测高转换的电路中，将信号通过到比主振荡器的信号低的频率之后产生这种占空比。

公开(公告)号：US5953253A

公开(公告)日：1999-09-14

申请号：US35654

申请日：1998-03-06

Applicant: Jean Devin ,  Bruno Leconte ,  Alessandro Brigati

Inventor： Jean Devin ,  Bruno Leconte ,  Alessandro Brigati

IPC: G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/28 ,  G11C16/3454 ,  G11C29/028 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5004

Abstract: An electrically programmable non-volatile memory organized in n-bit words includes a generator circuit to produce a verification voltage to perform a verification of a word in the memory. The generator circuit adjusts the verification voltage as a function of an information element that corresponds to the word to be verified.

Abstract translation: 以n比特字组织的电可编程非易失性存储器包括产生验证电压以产生存储器中的单词的验证的发生器电路。 发生器电路根据与要验证的单词相对应的信息元素来调整验证电压。

公开(公告)号：US5870336A

公开(公告)日：1999-02-09

申请号：US957666

申请日：1997-10-24

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C7/14 ,  G11C16/06

CPC classification number: G11C7/14

Abstract: To improve the reading time of a memory, it is determined when a word line will be completely charged by making an additional memory cell, connected to an additional bit line, at the end of this word line. The additional memory cells are all in a programming state such that they enable the detection of a read current positively. Furthermore, by programming these cells insufficiently, they become conductive before the normal cells of the memory array. This instant is used to activate the reading of the cells of the memory array.

Abstract translation: 为了提高存储器的读取时间，通过在该字线的末尾设置连接到附加位线的附加存储单元来确定字线何时完全充电。 附加存储器单元都处于编程状态，使得它们能够正确地检测读取电流。 此外，通过不充分地编程这些细胞，它们在存储器阵列的正常细胞之前变得导电。 该瞬间用于激活存储器阵列的单元的读取。