公开(公告)号：US06566736B1

公开(公告)日：2003-05-20

申请号：US09998624

申请日：2001-11-30

申请人： Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

发明人： Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

IPC分类号： H01L23544

CPC分类号： H01L23/564 ,  H01L23/3185 ,  H01L23/485 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/45144 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

摘要翻译： 公开了用于保护半导体器件免受湿气的湿度密封装置和方法。 在上绝缘体层和模具密封金属结构的暴露部分上形成诸如SiN的上密封层，以便在半导体器件中的电气部件和周围环境之间形成垂直的湿气密封。 横向密封件可以由装置中的上金属层中的模具密封金属结构和从模具密封金属向下延伸到基板或下模密封金属结构的一个或多个触点形成。

公开(公告)号：US08802537B1

公开(公告)日：2014-08-12

申请号：US11189874

申请日：2005-07-27

申请人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

发明人： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/02057

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。 在沟槽的相对侧上修整氮化物层。 在沟槽中形成衬里氧化物层。

公开(公告)号：US08476156B1

公开(公告)日：2013-07-02

申请号：US13338405

申请日：2011-12-28

申请人： Yider Wu ,  Hung-Wei Chen

发明人： Yider Wu ,  Hung-Wei Chen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

摘要翻译： 在具有应力区域的闪存结构的制造方法中，通过控制形成在栅极结构中并与硅衬底接触的隧道氧化物层的制造工艺，可以获得更好的应力效应，使得L形间隔物 （或第一应力区域）和每个L形间隔物的接触蚀刻停止层（或第二应力区域）形成在两个栅极结构之间并且彼此对准以增强栅极结构的载流子迁移率，从而 实现改善读取电流的效果，通过使用较低的读取电压获得所需的读取电流，减少产生应力引起的漏电流的可能性，以及增强闪速存储器的数据保存。

公开(公告)号：US07939423B2

公开(公告)日：2011-05-10

申请号：US12761460

申请日：2010-04-16

申请人： Yider Wu

发明人： Yider Wu

IPC分类号： H01L21/76

CPC分类号： H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

摘要翻译： 非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。 在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺， 浮动门和选择门同时形成。 因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。

公开(公告)号：US20100230738A1

公开(公告)日：2010-09-16

申请号：US12400828

申请日：2009-03-10

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/00

CPC分类号： H01L27/11521 ,  H01L29/40114 ,  H01L29/42324

摘要： In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

摘要翻译： 在制造NOR闪速存储器结构的方法中，执行高掺杂离子注入工艺以形成与轻掺杂漏极区重叠的高度掺杂的漏极区。 因此，在用于形成接触孔的蚀刻工艺期间，闪速存储器结构可以具有减小的漏极结深度以改善短沟道效应，同时保护轻掺杂漏极区域不被穿孔。

公开(公告)号：US07632749B1

公开(公告)日：2009-12-15

申请号：US10823970

申请日：2004-04-13

申请人： Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

发明人： Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14

摘要： A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

摘要翻译： 公开并提供了半导体器件。 半导体器件包括具有周边区域和中心区域的焊盘金属层。 此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。 此外，在焊盘金属层和下金属层之间形成层间电介质。 在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。 通孔电连接焊盘金属层和下部金属层。 另外，通孔位于垫金属层的周边区域的下方。

公开(公告)号：US07408220B2

公开(公告)日：2008-08-05

申请号：US11463250

申请日：2006-08-08

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US20070026609A1

公开(公告)日：2007-02-01

申请号：US11463250

申请日：2006-08-08

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07157333B1

公开(公告)日：2007-01-02

申请号：US11180117

申请日：2005-07-11

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07078749B1

公开(公告)日：2006-07-18

申请号：US10618156

申请日：2003-07-11

申请人： Jean Yee-Mei Yang ,  Yider Wu

发明人： Jean Yee-Mei Yang ,  Yider Wu

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G02F1/1334 ,  H01L29/792

摘要： According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.

摘要翻译： 根据一个实施例，存储器结构包括具有位于源极区域和漏极区域之间的沟道区域的衬底。 存储器结构还包括形成在衬底的沟道区上的栅极层和形成在栅极层和衬底上的可调谐层间电介质。 可调谐层间电介质具有透明状态和不透明状态，并且包括位于基体内的矩阵和电或磁性可调谐材料。 在透明状态期间，紫外线可以通过可调谐层间电介质到达栅极层，例如进行UV擦除操作。 在不透明状态期间，防止紫外线通过可调谐层间电介质到栅极层，从而保护栅极层免于不必要的电荷存储和在各种过程中可能发生的外在损伤。