公开(公告)号：US20070259493A1

公开(公告)日：2007-11-08

申请号：US11745059

申请日：2007-05-07

申请人： KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

发明人： KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

摘要翻译： 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US20070010055A1

公开(公告)日：2007-01-11

申请号：US11180117

申请日：2005-07-11

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一介电层之间形成多个第一导电层。

公开(公告)号：US07408220B2

公开(公告)日：2008-08-05

申请号：US11463250

申请日：2006-08-08

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US20070026609A1

公开(公告)日：2007-02-01

申请号：US11463250

申请日：2006-08-08

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07157333B1

公开(公告)日：2007-01-02

申请号：US11180117

申请日：2005-07-11

申请人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

发明人： Jongoh Kim ,  Yider Wu ,  Kent-Kuohua Chang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568

摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.

摘要翻译： 提供了一种制造非易失性存储器的方法。 在衬底上形成多个隔离结构的列。 在衬底上形成多个跨越隔离结构的层叠栅极结构的行。 在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。 在堆叠栅极结构的侧壁上形成多个隔离条。 多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。 此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。 在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

公开(公告)号：US07344938B2

公开(公告)日：2008-03-18

申请号：US11745059

申请日：2007-05-07

申请人： Kent Kuohua Chang ,  Jongoh Kim ,  Yider Wu

发明人： Kent Kuohua Chang ,  Jongoh Kim ,  Yider Wu

IPC分类号： H01L21/8244

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

摘要翻译： 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US07229876B2

公开(公告)日：2007-06-12

申请号：US11138612

申请日：2005-05-25

申请人： Kent Kuohua Chang ,  Jongoh Kim ,  Yider Wu

发明人： Kent Kuohua Chang ,  Jongoh Kim ,  Yider Wu

IPC分类号： H01L21/8244

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

摘要翻译： 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US20060270142A1

公开(公告)日：2006-11-30

申请号：US11138612

申请日：2005-05-25

申请人： Kent Chang ,  Jongoh Kim ,  Yider Wu

发明人： Kent Chang ,  Jongoh Kim ,  Yider Wu

IPC分类号： H01L21/8244

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

摘要翻译： 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US20140332844A1

公开(公告)日：2014-11-13

申请号：US13892191

申请日：2013-05-10

申请人： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

发明人： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L21/265 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7827

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括多个沟槽，每个沟槽具有沟槽端点，端点侧壁垂直于沟槽的纵向方向并且从顶表面垂直向下延伸到沟槽底表面。 半导体功率器件还包括设置在沟槽底表面下方的沟槽底部掺杂剂区域和沿端点侧壁设置的侧壁掺杂剂区域，其中侧壁掺杂剂区域沿着沟槽的端点侧壁垂直向下延伸以到达沟槽底部掺杂剂区域，并且 将沟槽底部掺杂剂区域拾取到半导体衬底的顶表面。

公开(公告)号：US08076708B2

公开(公告)日：2011-12-13

申请号：US12403602

申请日：2009-03-13

申请人： Yi-Hung Li ,  Jen-Chuan Pan ,  Jongoh Kim

发明人： Yi-Hung Li ,  Jen-Chuan Pan ,  Jongoh Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.

摘要翻译： 通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。 为低压晶体管形成具有第二厚度的第一栅介质层。 形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。 沉积并图案化多晶硅以限定字线和晶体管栅极。 第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。