公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US07518843B2

公开(公告)日：2009-04-14

申请号：US11134539

申请日：2005-05-19

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H02H9/00 ,  H02H3/22

CPC classification number: H01L27/0262

Abstract: An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

Abstract translation: ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。 具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。 可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。 在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

公开(公告)号：US07518192B2

公开(公告)日：2009-04-14

申请号：US10985532

申请日：2004-11-10

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC: H01L23/62

CPC classification number: H01L21/76816 ,  H01L27/0274 ,  H01L29/78

Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

Abstract translation: 提出了一种用于静电放电保护的半导体结构。 半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。 在源极和漏极侧形成多个接触插塞。 多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。 第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

公开(公告)号：US07508639B2

公开(公告)日：2009-03-24

申请号：US11305983

申请日：2005-12-19

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H02H9/00 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

Abstract translation: 提供具有ESD保护鲁棒性的输入/输出设备。 输入/输出装置包括输入/​​输出焊盘，第一NMOS晶体管，第二NMOS晶体管和ESD检测器。 第一NMOS晶体管包括第一漏极，第一源极和第一栅极，其中第一源极和第一栅极耦合到第一接地电源轨，第一漏极耦合到输入/输出焊盘。 第二NMOS晶体管包括第二漏极，第二源极和第二栅极，其中第二源极耦合到第一接地电源轨，第二漏极耦合到输入/输出焊盘，第二栅极耦合到第一预驱动器 。 当检测到ESD事件时，ESD检测器使第一预驱动器将第二栅极耦合到第一接地电源轨，由此第一和第二晶体管均匀地放电ESD电流。

公开(公告)号：US07485930B2

公开(公告)日：2009-02-03

申请号：US11622574

申请日：2007-01-12

Applicant: Jian-Hsing Lee ,  Shui-Hunyi Chen

Inventor： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract translation: 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07465994B2

公开(公告)日：2008-12-16

申请号：US11512850

申请日：2006-08-29

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

Abstract translation: ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20080211027A1

公开(公告)日：2008-09-04

申请号：US11713193

申请日：2007-03-01

Applicant: Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

Inventor： Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.

Abstract translation: 一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域 在第一N阱之外，但在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上 第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远 从第一个Nwell比NMOS晶体管。

公开(公告)号：US20080137244A1

公开(公告)日：2008-06-12

申请号：US11637108

申请日：2006-12-12

Applicant: Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

Inventor： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

IPC: H02H9/00

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.

Abstract translation: 静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。 此外，MOS触发装置没有物理地设置在SCR装置中。

公开(公告)号：US07372083B2

公开(公告)日：2008-05-13

申请号：US11199662

申请日：2005-08-09

Applicant: Jian-Hsing Lee ,  Yu-Chang Jong

Inventor： Jian-Hsing Lee ,  Yu-Chang Jong

IPC: H01L29/72

CPC classification number: H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

Abstract: A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

Abstract translation: 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US07179691B1

公开(公告)日：2007-02-20

申请号：US10207545

申请日：2002-07-29

Applicant: Jian-Hsing Lee ,  Shui Hun Yi Chen

Inventor： Jian-Hsing Lee ,  Shui Hun Yi Chen

IPC: H01L21/332 ,  H01L21/331

CPC classification number: H01L27/0255

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract translation: 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护装置和Vcc至Vss保护装置的重掺杂P +保护环组成。 此外，还有一个围绕I / O保护器件及其P +保护环的重掺杂N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。