公开(公告)号：US20090127609A1

公开(公告)日：2009-05-21

申请号：US12232020

申请日：2008-09-10

申请人： Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

发明人： Sung-Hee Han ,  Jin-Woo Lee ,  Tae-Young Chung ,  Ja-Young Lee

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/3247 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/78

摘要： Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

摘要翻译： 提供一种制造凹槽通道晶体管和相关半导体器件的方法。 该方法可以包括在衬底上形成第一栅极沟槽，在第一栅极沟槽的侧壁上形成电介质间隔物，在第一栅极沟槽下面的衬底上形成第二栅极沟槽，以及形成栅电极以填充沟槽。 电介质隔离物可以保留在栅电极和衬底之间。

公开(公告)号：US20080169493A1

公开(公告)日：2008-07-17

申请号：US11809252

申请日：2007-05-31

申请人： Jin-Woo Lee ,  Tae-Young Chung

发明人： Jin-Woo Lee ,  Tae-Young Chung

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L27/10876 ,  H01L29/1041 ,  H01L29/42376 ,  H01L29/66621

摘要： Semiconductor devices include an active region defined in a semiconductor substrate having first type impurity ions. A retrograde region is in the active region and has second type impurity ions. An upper channel region is on the retrograde region in the active region and has the first type impurity ions. Source and drain regions are on the upper channel region in the active region and spaced apart from each other. A gate electrode fills a gate trench formed in the active region. The gate electrode is disposed between the source and drain regions and extends into the retrograde region through the upper channel region. DRAM devices and methods are also provided.

摘要翻译： 半导体器件包括限定在具有第一类型杂质离子的半导体衬底中的有源区。 逆行区位于有源区并具有第二类杂质离子。 上通道区域在有源区域的逆行区域上，并具有第一类杂质离子。 源极和漏极区域在有源区域中的上部沟道区域上并且彼此间隔开。 栅电极填充形成在有源区中的栅极沟槽。 栅电极设置在源区和漏区之间，并通过上沟道区延伸到逆行区。 还提供DRAM装置和方法。

公开(公告)号：US07670910B2

公开(公告)日：2010-03-02

申请号：US11641845

申请日：2006-12-20

申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

公开(公告)号：US07476585B2

公开(公告)日：2009-01-13

申请号：US11621507

申请日：2007-01-09

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC分类号： H01L21/8239

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US07279741B2

公开(公告)日：2007-10-09

申请号：US10845688

申请日：2004-05-13

申请人： Chang-Hyun Cho ,  Soo-Ho Shin ,  Yong-Gyu Choi ,  Tae-Young Chung

发明人： Chang-Hyun Cho ,  Soo-Ho Shin ,  Yong-Gyu Choi ,  Tae-Young Chung

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6656

摘要： A semiconductor device with an increased effective channel length and a method of manufacturing the same. The device includes a semiconductor substrate, a gate insulating layer disposed on the semiconductor substrate, a gate electrode structure disposed on a predetermined portion of the gate insulating layer, an insulating layer for preventing short channel disposed on the surface of the resultant structure where the gate electrode structure is disposed, and a source region and a drain region disposed in the semiconductor substrate on either side of the gate electrode structure. Both the source region and the drain region are spaced apart from the gate electrode structure by the thickness of the insulating layer. The channel length of a MOS transistor can be thereby increased.

摘要翻译： 具有增加的有效通道长度的半导体器件及其制造方法。 该器件包括半导体衬底，设置在半导体衬底上的栅极绝缘层，设置在栅极绝缘层的预定部分上的栅极电极结构，用于防止短路通道的绝缘层，所述绝缘层设置在所述结构的表面上， 电极结构，以及设置在栅电极结构的任一侧的半导体衬底中的源区和漏区。 源极区域和漏极区域与栅电极结构隔开绝缘层的厚度。 可以提高MOS晶体管的沟道长度。

公开(公告)号：US07205232B2

公开(公告)日：2007-04-17

申请号：US10846810

申请日：2004-05-13

申请人： Cheol-Ju Yun ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Tae-Young Chung

IPC分类号： H01L21/44 ,  H01L23/52

CPC分类号： H01L21/76897 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a method of forming a self-aligned contact structure using a sacrificial mask layer. The method includes forming a plurality of parallel interconnection patterns on a semiconductor substrate. Each of the interconnection patterns has an interconnection and a mask pattern, which are sequentially stacked. Interlayer insulating layer patterns are formed to fill gap regions between the interconnection patterns. The mask patterns are partially etched to form recessed mask patterns that define grooves between the interlayer insulating layer patterns. Then, sacrificial mask patterns filling the grooves are formed. A predetermined region of the interlayer insulating layer patterns is etched using the sacrificial mask patterns as etching masks to form a self-aligned contact hole that exposes a predetermined region of the semiconductor substrate. A spacer is formed of a sidewall of the self-aligned contact hole, and a plug surrounded by the spacer is formed in the self-aligned contact hole.

摘要翻译： 公开了使用牺牲掩模层形成自对准接触结构的方法。 该方法包括在半导体衬底上形成多个平行互连图案。 每个互连图案具有顺序堆叠的互连和掩模图案。 形成层间绝缘层图案以填充互连图案之间的间隙区域。 掩模图案被部分蚀刻以形成在层间绝缘层图案之间限定凹槽的凹陷掩模图案。 然后，形成填充凹槽的牺牲掩模图案。 使用牺牲掩模图案作为蚀刻掩模蚀刻层间绝缘层图案的预定区域，以形成暴露半导体基板的预定区域的自对准接触孔。 间隔件由自对准接触孔的侧壁形成，并且在自对准接触孔中形成由间隔件围绕的塞子。

公开(公告)号：US20060205147A1

公开(公告)日：2006-09-14

申请号：US11430036

申请日：2006-05-09

申请人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC分类号： H01L21/8242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

摘要翻译： 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US20050046048A1

公开(公告)日：2005-03-03

申请号：US10762380

申请日：2004-01-23

申请人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

摘要翻译： 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US06229171B1

公开(公告)日：2001-05-08

申请号：US09347823

申请日：1999-07-02

申请人： Yoon-Soo Chun ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Yoon-Soo Chun ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L27/10852

摘要： A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

摘要翻译： 具有用于半导体器件的高电介质膜的堆叠电容器的存储元件及其制造方法，所述存储元件具有存储节点，所述存储节点包括底部多晶硅层，阻挡金属层和具有侧壁间隔物的过渡金属层 形成在阻挡金属层上。 阻挡金属层和侧壁间隔物防止多晶硅层被氧化。 多晶硅层形成为确定存储节点的高度的厚度。 直接连接高电介质膜的过渡金属层被薄形成，以避免其斜坡蚀刻，从而防止相邻存储节点之间的电桥或短路。

公开(公告)号：US07388243B2

公开(公告)日：2008-06-17

申请号：US11430036

申请日：2006-05-09

申请人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

发明人： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC分类号： H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

摘要： A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

摘要翻译： 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。