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31.发明申请公开(公告)号：US20090249301A1
公开(公告)日：2009-10-01
申请号：US12059897
申请日：2008-03-31
IPC分类号： G06F11/36
CPC分类号： G06F11/3668
摘要： Techniques are provided for determining consequences of an injected fault on a system running a given application program or operating system, in order to measure the software impact of a hardware soft error on the application program/operating system. The application program software is emulated instruction-by-instruction, where source operands are randomly modified before an instruction is executed, and destination operands are randomly modified after an instruction is executed, in order to mimic hardware soft errors. In addition, a program counter is randomly modified after execution of a branch instruction. The resulting consequences of such modifications are monitored such that a fault of an instruction being executed is modeled in order to determine a soft error rate (SER) for a software application program or operating system.
摘要翻译： 提供了用于确定注入的故障对运行给定应用程序或操作系统的系统的后果的技术，以便测量硬件软错误对应用程序/操作系统的软件影响。 应用程序软件被仿真逐个指令，其中在执行指令之前对源操作数进行随机修改，并且在执行指令之后随机修改目的地操作数，以模拟硬件软错误。 此外，在执行分支指令之后，程序计数器被随机地修改。 监视这种修改产生的后果，以便对所执行的指令的故障进行建模，以确定软件应用程序或操作系统的软错误率（SER）。
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32.发明申请METHOD, SYSTEM, AND PRODUCT FOR PROGRAMMING IN A SIMULTANEOUS MULTI-THREADED PROCESSOR ENVIRONMENT 失效同时多线程处理器环境中编程的方法，系统和产品公开(公告)号：US20080189704A1
公开(公告)日：2008-08-07
申请号：US12107239
申请日：2008-04-22
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/52 , G06F11/3688
摘要： A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.
摘要翻译： 公开了同时测试多个线程的系统，方法和产品。 线程共享一个真正的内存空间。 实际存储器空间的第一部分被指定为排他存储器，使得第一部分似乎被保留仅由一个线程使用。 线程同时执行。 线程在执行期间访问第一部分。 第一个线程允许对真实存储器空间的第一部分的明显的独占使用。 同时允许第一个线程明确地使用第一部分，实际存储器空间的第一部分的明显独占使用也可以由第二个线程允许。 线程同时似乎具有第一部分的独占使用，并且可以同时访问第一部分。
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33.发明授权Applications of operating mode dependent error signal generation upon real address range checking prior to translation 有权在翻译之前的实际地址范围检查中应用与操作模式相关的误差信号生成公开(公告)号：US06829684B2
公开(公告)日：2004-12-07
申请号：US10175626
申请日：2002-06-20
申请人： Richard William Doing , Ronald Nick Kalla , Stephen Joseph Schwinn , Edward John Silha , Kenichi Tsuchiya
发明人： Richard William Doing , Ronald Nick Kalla , Stephen Joseph Schwinn , Edward John Silha , Kenichi Tsuchiya
IPC分类号： G06F1214
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/5077 , G06F12/0284 , G06F12/1036 , G06F12/109 , G06F12/1491
摘要： A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer system's hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.
摘要翻译： 实际的地址范围检查机制验证计算机系统中产生的真实地址，其中可以从有效地址转换实际地址，一些有效地址是不需要翻译的实际地址。 系统至少有两种操作模式。 在一种模式中，范围检查机构响应于检测到超出预定范围的实际地址产生误差信号，而在其它操作模式中，不产生误差信号。 优选地，计算机系统的硬件资源（包括实际地址空间）在逻辑上被分区，由被称为管理程序的超特权进程管理分区。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，虚拟机管理程序状态中的实际地址范围检查错误信号被禁用。
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34.发明授权Thread switch tuning tool for optimal performance in a computer processor 失效线程切换调谐工具，可在计算机处理器中实现最佳性能
公开(公告)号：US06018759A
公开(公告)日：2000-01-25
申请号：US996309
申请日：1997-12-22
CPC分类号： G06F9/4843 , G06F11/3414 , G06F9/3009 , G06F9/3851 , G06F11/3409 , G06F11/3428 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method, apparatus, and article of manufacture for performing thread switch tuning for optimal performance of a program executed by a computer data processing system having a multithreaded processor. The system includes a performance monitor facility; a thread switch controller enabling thread switching for the target program while the target program is executed and disabling thread switching after completing execution of the target program; a thread switch control register including at least one thread switching event for the target program; a monitor for monitoring performance of the target program by the performance monitor facility to measure and record the performance, setting a different value for the thread switch control register whereby the target program is executed for the plurality of times, each time with a different value for the thread switch control register, choosing one of the values of the thread switch control register, after completing execution of the target program for the plurality of times, as an optimal value of the thread switch control register for the target program, based on a highest performance recorded by the performance monitor facility.
摘要翻译： 一种用于执行线程切换调谐以便由具有多线程处理器的计算机数据处理系统执行的程序的最佳性能的方法，装置和制品。 该系统包括一个性能监视器; 螺纹开关控制器，在执行目标程序时，使能目标程序的线程切换，并且在完成执行目标程序之后禁用线程切换; 线程开关控制寄存器，其包括用于所述目标程序的至少一个线程切换事件; 监视器，用于通过性能监视器设备监视目标程序的性能，以测量和记录性能，为线程切换控制寄存器设置不同的值，由此目标程序执行多次，每次具有不同的值 线程开关控制寄存器，在完成目标程序执行多次之后，选择线程切换控制寄存器的值之一，作为目标程序的线程切换控制寄存器的最佳值，基于最高 性能监测仪器记录的性能。
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