公开(公告)号：US07465613B2

公开(公告)日：2008-12-16

申请号：US11616542

申请日：2006-12-27

申请人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

发明人： Jong-Hyun Choung ,  Hong-Sick Park ,  Joo-Ae Youn ,  Sun-Young Hong ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Doo-Hee Jung ,  Byeong-Jin Lee

IPC分类号： H01L21/00 ,  H01L21/84

摘要： A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

公开(公告)号：US07435629B2

公开(公告)日：2008-10-14

申请号：US11207522

申请日：2005-08-19

申请人： Joo-Ae Youn

发明人： Joo-Ae Youn

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124

摘要： A method of manufacturing a thin film transistor array panel and a thin film transistor array panel are provided. The method includes: forming a gate line and a storage electrode line on a substrate; forming a gate insulating layer on the gate line and the storage electrode line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; forming a photoresist including a first portion and a second portion on the passivation layer; etching the passivation layer using the photoresist to expose a portion of the data line and a first portion of the gate insulating layer; removing the second portion of the photoresist; etching the passivation layer and the first portion of the gate insulating layer using the photoresist to expose a second portion of the gate insulating layer and a portion of the drain electrode and a portion of the gate line; depositing a conductive film on the first transformed photoresist; and removing the first transformed photoresist to form a pixel electrode connected to the exposed portion of the drain electrode.

摘要翻译： 提供了制造薄膜晶体管阵列面板和薄膜晶体管阵列面板的方法。 该方法包括：在基板上形成栅极线和存储电极线; 在栅极线和存储电极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 在所述钝化层上形成包括第一部分和第二部分的光致抗蚀剂; 使用所述光致抗蚀剂蚀刻所述钝化层以暴露所述数据线的一部分和所述栅极绝缘层的第一部分; 去除光致抗蚀剂的第二部分; 使用所述光致抗蚀剂蚀刻所述钝化层和所述栅极绝缘层的所述第一部分，以暴露所述栅极绝缘层的第二部分以及所述漏极电极的一部分和所述栅极线的一部分; 在第一转换的光致抗蚀剂上沉积导电膜; 以及去除所述第一变换的光致抗蚀剂以形成连接到所述漏电极的所述暴露部分的像素电极。

公开(公告)号：US20110014737A1

公开(公告)日：2011-01-20

申请号：US12890324

申请日：2010-09-24

申请人： Jong-Hyun CHOUNG ,  Hong-Sick Park ,  Joo-Ae Youn ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

发明人： Jong-Hyun CHOUNG ,  Hong-Sick Park ,  Joo-Ae Youn ,  Bong-Kyun Kim ,  Won-Suk Shin ,  Byeong-Jin Lee

IPC分类号： H01L21/8234

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/4908

摘要： A thin film transistor array and method of manufacturing the same include a pixel electrode formed of a transparent conductive layer on a substrate, a gate line formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate electrode connected to the gate line and formed of the transparent conductive layer and an opaque conductive layer on the substrate, a gate insulating layer which covers the gate line and the gate electrode, a semiconductor layer formed on the gate insulating layer to overlap the gate electrode, a data line which intersects the gate line, a source electrode connected to the data line to overlap a part of the semiconductor layer, and a drain electrode connected to the pixel electrode to overlap a part of the semiconductor layer.

摘要翻译： 薄膜晶体管阵列及其制造方法包括由基板上的透明导电层形成的像素电极，由透明导电层形成的栅极线和基板上的不透明导电层，连接到栅极的栅电极 并且在基板上形成透明导电层和不透明导电层，覆盖栅极线和栅极的栅极绝缘层，形成在栅极绝缘层上以与栅电极重叠的半导体层，数据线， 与栅极线相交，连接到数据线的源电极与半导体层的一部分重叠，以及连接到像素电极以与半导体层的一部分重叠的漏电极。

公开(公告)号：US07662651B2

公开(公告)日：2010-02-16

申请号：US11695937

申请日：2007-04-03

申请人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Yeong Lee

发明人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Yeong Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/124

摘要： A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

摘要翻译： 在基板上形成具有栅电极的多条栅极线，在覆盖栅极线的栅极绝缘层上形成半导体层。 在栅极绝缘层上形成与栅极线相交的多个数据线，并且形成与数据线平行且相邻延伸的多个漏电极。 此外，多个保持电容导体形成为连接到漏极并与相邻的栅极线重叠。 在上述结构上形成由有机材料制成的钝化层，并具有接触孔。 此外，形成多个像素电极，以通过接触孔电连接到漏电极。

公开(公告)号：US20080268581A1

公开(公告)日：2008-10-30

申请号：US12009253

申请日：2008-01-16

申请人： Hong-Kee Chin ,  Yu-Gwang Jeong ,  Sang-Gab Kim ,  Joo-Han Kim ,  Joo-Ae Youn ,  Min-Seok Oh ,  Jong-Hyun Choung ,  Seung-Ha Choi

发明人： Hong-Kee Chin ,  Yu-Gwang Jeong ,  Sang-Gab Kim ,  Joo-Han Kim ,  Joo-Ae Youn ,  Min-Seok Oh ,  Jong-Hyun Choung ,  Seung-Ha Choi

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a TFT substrate includes: sequentially forming a transparent conductive layer and an opaque conductive layer on a substrate, patterning the transparent conductive layer and the opaque conductive layer by using a first mask to form a gate pattern including a pixel electrode, and forming a gate insulating layer and a semiconductor layer above the substrate. A contact hole is formed which exposes a portion of the pixel electrode and a semiconductor pattern using a second mask. A conductive layer is formed above the substrate and patterned to form a source/drain pattern including a drain electrode which overlaps a portion of the pixel electrode. Portions of the gate insulating layer and the opaque conductive layer above the pixel electrode are removed except a portion overlapping the drain electrode, by using a third mask.

摘要翻译： 一种制造TFT基板的方法包括：在基板上依次形成透明导电层和不透明导电层，通过使用第一掩模对透明导电层和不透明导电层进行构图，形成包括像素电极的栅极图案，以及 在基板上形成栅极绝缘层和半导体层。 使用第二掩模形成露出一部分像素电极和半导体图案的接触孔。 在衬底上形成导电层，并被图案化以形成包括与像素电极的一部分重叠的漏电极的源极/漏极图案。 除了与漏电极重叠的部分之外，通过使用第三掩模除去栅极绝缘层和像素电极上方的不透明导电层的部分。

公开(公告)号：US20080237597A1

公开(公告)日：2008-10-02

申请号：US12043615

申请日：2008-03-06

申请人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

发明人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

IPC分类号： H01L29/04 ,  H01L27/12 ,  H01L31/036

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/78696

摘要： A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

摘要翻译： TFT阵列面板包括：彼此连接的第一和第二栅极部件; 形成在所述第一和第二栅极部件上的栅极绝缘层; 第一和第二半导体部件分别形成在与第一和第二栅极部件相对的栅极绝缘层上; 第一和第二源元件分别彼此连接并位于第一和第二半导体元件附近; 分别位于第一和第二半导体构件附近并分别相对于第一和第二栅极构件相对于第一和第二源构件定位的第一和第二漏极构件; 以及连接到第一和第二漏极部件的像素电极。 第一栅极，半导体，源极和漏极部件形成第一TFT，第二栅极，半导体，源极和漏极部件形成第二TFT。

公开(公告)号：US07358124B2

公开(公告)日：2008-04-15

申请号：US11516187

申请日：2006-09-06

申请人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

发明人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/78696

摘要： A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

摘要翻译： TFT阵列面板包括：彼此连接的第一和第二栅极部件; 形成在所述第一和第二栅极部件上的栅极绝缘层; 第一和第二半导体部件分别形成在与第一和第二栅极部件相对的栅极绝缘层上; 第一和第二源元件分别彼此连接并位于第一和第二半导体元件附近; 分别位于第一和第二半导体构件附近并分别相对于第一和第二栅极构件相对于第一和第二源构件定位的第一和第二漏极构件; 以及连接到第一和第二漏极部件的像素电极。 第一栅极，半导体，源极和漏极部件形成第一TFT，第二栅极，半导体，源极和漏极部件形成第二TFT。

公开(公告)号：US07288790B2

公开(公告)日：2007-10-30

申请号：US11612055

申请日：2006-12-18

申请人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

发明人： Young-Mi Tak ,  Seung-Soo Baek ,  Joo-Ae Youn ,  Dong-Gyu Kim

IPC分类号： H01L29/04 ,  H01L31/20 ,  H01L31/036 ,  H01L31/0376

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/78696

摘要： A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

摘要翻译： TFT阵列面板包括：彼此连接的第一和第二栅极部件; 形成在所述第一和第二栅极部件上的栅极绝缘层; 第一和第二半导体部件分别形成在与第一和第二栅极部件相对的栅极绝缘层上; 第一和第二源元件分别彼此连接并位于第一和第二半导体元件附近; 分别位于第一和第二半导体构件附近并分别相对于第一和第二栅极构件相对于第一和第二源构件定位的第一和第二漏极构件; 以及连接到第一和第二漏极部件的像素电极。 第一栅极，半导体，源极和漏极部件形成第一TFT，第二栅极，半导体，源极和漏极部件形成第二TFT。

公开(公告)号：US07214965B2

公开(公告)日：2007-05-08

申请号：US11010151

申请日：2004-12-10

申请人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Young Lee

发明人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Young Lee

IPC分类号： H01L29/04 ,  H01L29/15

CPC分类号： H01L27/124

摘要： A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

摘要翻译： 在基板上形成具有栅电极的多条栅极线，在覆盖栅极线的栅极绝缘层上形成半导体层。 在栅极绝缘层上形成与栅极线相交的多个数据线，并且形成与数据线平行且相邻延伸的多个漏电极。 此外，多个保持电容导体形成为连接到漏极并与相邻的栅极线重叠。 在上述结构上形成由有机材料制成的钝化层，并具有接触孔。 此外，形成多个像素电极，以通过接触孔电连接到漏电极。

公开(公告)号：US20050167669A1

公开(公告)日：2005-08-04

申请号：US11010151

申请日：2004-12-10

申请人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Young Lee

发明人： Kyung-Wook Kim ,  Joo-Ae Youn ,  Seong-Young Lee

IPC分类号： G02F1/1368 ,  G02F1/136 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： H01L27/124

摘要： A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

摘要翻译： 在基板上形成具有栅电极的多条栅极线，在覆盖栅极线的栅极绝缘层上形成半导体层。 在栅极绝缘层上形成与栅极线相交的多个数据线，并且形成与数据线平行且相邻延伸的多个漏电极。 此外，多个保持电容导体形成为连接到漏极并与相邻的栅极线重叠。 在上述结构上形成由有机材料制成的钝化层，并具有接触孔。 此外，形成多个像素电极，以通过接触孔电连接到漏电极。