公开(公告)号：US06537861B1

公开(公告)日：2003-03-25

申请号：US09382108

申请日：1999-08-24

申请人： Karl-Eugen Kroell ,  Juergen Pille ,  Helmut Schettler

发明人： Karl-Eugen Kroell ,  Juergen Pille ,  Helmut Schettler

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L29/7841 ,  H01L29/78615

摘要： An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.

摘要翻译： 提供SOI场效应晶体管，其包括由形成在晶体管的主体部分中的浅沟槽隔离的体接触，从而消除栅极电容或延迟的任何增加。 提供了一种形成这种晶体管的方法，其不需要任何额外的工艺步骤。

公开(公告)号：US06341093B1

公开(公告)日：2002-01-22

申请号：US09872885

申请日：2001-06-01

申请人： Martin Eckert ,  Guenter Mayer ,  Juergen Pille ,  Dieter Wendel

发明人： Martin Eckert ,  Guenter Mayer ,  Juergen Pille ,  Dieter Wendel

IPC分类号： G11C2900

CPC分类号： G11C29/50 ,  G11C11/41

摘要： The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.

摘要翻译： 本发明涉及存储装置，特别涉及用于测试历史依赖存储器阵列单元的存储质量的方法。 可以用预定的测试条件选择性地对电池进行应力，使得这些测试条件覆盖当电池在全部工作条件下操作时可能出现的所有硬件状态分布。 这主要通过切断有效字线选择脉冲的后沿的预定截止宽度来实现。

公开(公告)号：US20100039876A1

公开(公告)日：2010-02-18

申请号：US12190242

申请日：2008-08-12

申请人： Chad A. Adams ,  Juergen Pille

发明人： Chad A. Adams ,  Juergen Pille

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/1204 ,  G11C2029/5006

摘要： A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge (PCHG) signals are provided with a high value. When selection is made from a top sub-group of SRAM cells, a corresponding bitline, “BLT_TOP”, takes a value which reflects a state stored in the selected cell. In addition, the bitline corresponding to the bottom sub-group of cells, “BLT_BOT”, takes a high value. If there is a leakage defect, BLT_BOT drops to a low value. With no leakage defect, the data stored in the selected cell is determined based on the result of a logical NAND operation including the respective states indicated by the BLT_TOP and by the BLT_BOT.

摘要翻译： 一种用于保持静态随机存取存储器（SRAM）功能的方法和系统，同时在浮动模式操作期间同时筛选从位线到地的泄漏路径。 SRAM配置允许SRAM单元选择进行读或写操作。 响应于SRAM单元选择，提供一组具有高值的预充电（PCHG）信号。 当从SRAM单元的顶部子组进行选择时，相应的位线“BLT_TOP”取反映存储在所选单元中的状态的值。 另外，对应于单元格底部子组“BLT_BOT”的位线取高值。 如果存在泄漏缺陷，BLT_BOT将降至低值。 在没有泄漏缺陷的情况下，基于包括由BLT_TOP指示的各个状态和BLT_BOT的逻辑NAND操作的结果来确定存储在所选择的单元中的数据。

公开(公告)号：US20090116307A1

公开(公告)日：2009-05-07

申请号：US11935741

申请日：2007-11-06

申请人： Scott R. Cottier ,  Sang Hoo Dhong ,  Rajiv V. Joshi ,  Juergen Pille ,  Osamu Takahashi

发明人： Scott R. Cottier ,  Sang Hoo Dhong ,  Rajiv V. Joshi ,  Juergen Pille ,  Osamu Takahashi

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/418

摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.

摘要翻译： 电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个 的操作。

公开(公告)号：US20050132319A1

公开(公告)日：2005-06-16

申请号：US10983819

申请日：2004-11-08

申请人： Ulrich Krauch ,  Juergen Pille ,  Tobias Werner ,  Alexander Woerner

发明人： Ulrich Krauch ,  Juergen Pille ,  Tobias Werner ,  Alexander Woerner

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

摘要翻译： 根据本发明，提供了一种用于布线和设计LSI（大规模集成电路）的自动化方法。 首先，要连接的书的实例的至少一个通用性位于芯片上，其中实例的通用是根据所述实例的测量定义的区域。 然后，通过根据给定的设计规则优化到相应通用的路由来生成到所述实例的初始路由。 因此，针对所述实例确定优化的引脚位置。 然后，基于所述优化的引脚位置，生成用于所述实例的布局来代替相应的通用。 最后，实际产生的引脚与初始路由的相应末端相连。

公开(公告)号：US20050128845A1

公开(公告)日：2005-06-16

申请号：US11051594

申请日：2005-02-04

申请人： Stefan Buettner ,  Jens Leenstra ,  Juergen Pille ,  Christian Schweizer

发明人： Stefan Buettner ,  Jens Leenstra ,  Juergen Pille ,  Christian Schweizer

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1075

摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

摘要翻译： 一种用于将地址字解码为字线信号的方法和装置。 多个地址线将地址字馈送到多个解码块，每个解码块与由用于产生相应字线信号的地址字形成的地址空间中的特定地址相关联，由此每个解码块连接到多个解码块 的地址线。 省略与由地址字形成的地址空间中的预定地址相关联的至少一个解码块，使得只要在多个地址线上输入预定的地址字，就不会将生成的字线切换到活动状态 。

公开(公告)号：US06873567B2

公开(公告)日：2005-03-29

申请号：US10636387

申请日：2003-08-07

申请人： Stefan Buettner ,  Jens Leenstra ,  Juergen Pille ,  Christian Schweizer

发明人： Stefan Buettner ,  Jens Leenstra ,  Juergen Pille ,  Christian Schweizer

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1075

摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

公开(公告)号：US06801069B1

公开(公告)日：2004-10-05

申请号：US09071912

申请日：1998-05-04

申请人： Robert R. Livolsi ,  Juergen Pille

发明人： Robert R. Livolsi ,  Juergen Pille

IPC分类号： H03K3356

CPC分类号： H03K3/356121 ,  H03K3/356156

摘要： A receiving latch with hysteresis circuit for receiving data on cross chip boundaries in a chip to chip interface has a clock section and a feed section and a hysteresis latch section with the feed section receiver enable input pin for a dataline passing through the receiver feed section and hysteresis latch section. The receiver enable input pin D is settable to a high or low voltage level, respectively turning the hysteresis latch section on said dataline ON or OFF. The hysteresis latch pass gate has clock couplings to the pgate and ngate of the PFET and NFET transistors of the pass gate. The drains of said pass gate PFET and NFET are coupled to ground and their sources to a positive potential provided over said data line. The drain of a latch PFET has its source connected to a positive potential and the source of an latch NFET has having its drain connected to ground and both the latch PFET and NFET have their gate connection to the dataline latch output for gating the dataline information out of the latch from the latch gates of the hysteresis latch section.

摘要翻译： 具有用于在芯片到芯片接口中的跨芯片边界上接收数据的滞后电路的接收锁存器具有时钟部分和馈电部分以及滞后锁存部分，馈电部分接收器使能输入引脚用于通过接收器馈电部分的数据线， 迟滞锁存部分。 接收器使能输入引脚D可设置为高或低电压电平，分别转动所述数据线上的迟滞锁存部分ON或OFF。 滞后锁存通路门具有与通孔的PFET和NFET晶体管的脉冲耦合的时钟耦合。 所述通栅PFET和NFET的漏极耦合到地和它们的源到在所述数据线上提供的正电位。 闩锁PFET的漏极的源极连接到正电位，并且锁存器NFET的源极具有连接到地的漏极，并且锁存器PFET和NFET都与栅极连接到数据线锁存器输出，用于门控数据信息输出 来自滞后锁存部分的锁存门的锁存器。

公开(公告)号：US06295232B2

公开(公告)日：2001-09-25

申请号：US09733328

申请日：2000-12-08

申请人： Juergen Pille ,  Klaus Helwig ,  Dieter Wendel

发明人： Juergen Pille ,  Klaus Helwig ,  Dieter Wendel

IPC分类号： G11C700

CPC分类号： G11C11/419 ,  G11C7/067

摘要： A read circuit for semiconductor storage cells (10, 50) including dual read bitlines (23, 24, 51, 52) driven by the cell to full ‘zero’ signals and ‘weak one’ signals comprises a read head circuit (53) which includes an inverter (56) in one of the bitlines (52). The inverter serves to turn a ‘weak one’ signal to a full ‘zero’ signal. A bit select circuit is integrated into the read head circuit (53) and connects the output of the inverter and the other one of the bitlines (51) through bit select switches (57, 58) to the single line output (XT1) of the read head circuit (53).

摘要翻译： 包括由单元驱动到完全“零”信号和“弱”信号的双重读取位线（23,24,51,52）的半导体存储单元（10,50）的读取电路包括一个读取头电路（53） 在位线（52）之一中包括逆变器（56）。 逆变器用于将“弱”信号转换为完全“零”信号。 一个位选择电路被集成到读取头电路53中，并通过位选择开关57,58将反相器的输出和位线51中的另一个通过位线选择开关57连接到单线输出（XT1） 读头电路（53）。

公开(公告)号：US07710796B2

公开(公告)日：2010-05-04

申请号：US11935741

申请日：2007-11-06

申请人： Scott R. Cottier ,  Sang Hoo Dhong ,  Rajiv V. Joshi ,  Juergen Pille ,  Osamu Takahashi

发明人： Scott R. Cottier ,  Sang Hoo Dhong ,  Rajiv V. Joshi ,  Juergen Pille ,  Osamu Takahashi

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/418

摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.

摘要翻译： 电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个 的操作。