公开(公告)号：US20230122500A1

公开(公告)日：2023-04-20

申请号：US17930300

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Tsuneo INABA ,  Keisuke NAKATSUKA ,  Takashi MAEDA

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/1158 ,  G11C5/06

Abstract: According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

公开(公告)号：US20220085003A1

公开(公告)日：2022-03-17

申请号：US17189955

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Takahiro TOMIMATSU ,  Ryo TANAKA

IPC: H01L25/18 ,  H01L23/00

Abstract: According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

公开(公告)号：US20210313335A1

公开(公告)日：2021-10-07

申请号：US17349103

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Kana HIRAYAMA ,  Yasuhiro UCHIYAMA ,  Keisuke NAKATSUKA

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

Abstract: According to one embodiment, a memory device includes a plurality of first conductors stacked along a first direction; a second, third, and fourth conductor stacked in a same layer above the first conductors; a plurality of fifth conductors stacked along the first direction; a sixth conductor stacked above the fifth conductors; a first semiconductor extending along the first direction between the second conductor and the sixth conductor; a second semiconductor extending along the first direction between the third conductor and the sixth conductor; and a third semiconductor extending along the first direction between the fourth conductor and the sixth conductor.

公开(公告)号：US20210296298A1

公开(公告)日：2021-09-23

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Hiroshi MAEJIMA ,  Kenichiro YOSHII ,  Takashi MAEDA ,  Hideo WADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.