公开(公告)号：US20230017218A1

公开(公告)日：2023-01-19

申请号：US17952718

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/762

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

公开(公告)号：US20210057446A1

公开(公告)日：2021-02-25

申请号：US16999149

申请日：2020-08-21

Applicant: Kioxia Corporation

Inventor： Ryosuke SAWABE ,  Yasuhiro UCHIYAMA ,  Hiroshi ITOKAWA

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C16/04

Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.

公开(公告)号：US20240064986A1

公开(公告)日：2024-02-22

申请号：US18497435

申请日：2023-10-30

Applicant: Kioxia Corporation

Inventor： Hiroshi NAKAKI ,  Yasuhiro UCHIYAMA

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: According to one embodiment, a memory device includes: a first conductive layer; a first conductive film extending in a first direction above the first conductive layer; a first semiconductor film extending in the first direction between the first conductive layer and the first conductive film and intersecting the first conductive layer; a second semiconductor film that is in contact with the first semiconductor film, extends in the first direction between the first conductive layer and the first conductive film, and faces the first conductive film; a first insulating film provided between the first conductive layer and the first semiconductor film; and a second insulating film provided between the first conductive film and each of the first semiconductor film and the second semiconductor film.

公开(公告)号：US20230282621A1

公开(公告)日：2023-09-07

申请号：US18316051

申请日：2023-05-11

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro UCHIYAMA

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L24/16 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2225/06524 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2924/1434

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.

公开(公告)号：US20230395500A1

公开(公告)日：2023-12-07

申请号：US18181851

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA

IPC: H01L23/528 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  H01L23/522 ,  H10B80/00 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H01L25/18

CPC classification number: H01L23/5283 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  H01L23/5226 ,  H10B80/00 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H01L25/18

Abstract: According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

公开(公告)号：US20210313335A1

公开(公告)日：2021-10-07

申请号：US17349103

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Kana HIRAYAMA ,  Yasuhiro UCHIYAMA ,  Keisuke NAKATSUKA

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

Abstract: According to one embodiment, a memory device includes a plurality of first conductors stacked along a first direction; a second, third, and fourth conductor stacked in a same layer above the first conductors; a plurality of fifth conductors stacked along the first direction; a sixth conductor stacked above the fifth conductors; a first semiconductor extending along the first direction between the second conductor and the sixth conductor; a second semiconductor extending along the first direction between the third conductor and the sixth conductor; and a third semiconductor extending along the first direction between the fourth conductor and the sixth conductor.

公开(公告)号：US20230320107A1

公开(公告)日：2023-10-05

申请号：US18330779

申请日：2023-06-07

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA ,  Akira MINO ,  Masayoshi TAGAMI ,  Shinya ARAI

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  G11C16/0483 ,  G11C16/26 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

公开(公告)号：US20230116382A1

公开(公告)日：2023-04-13

申请号：US18079364

申请日：2022-12-12

Applicant: Kioxia Corporation

Inventor： Yasuhiro UCHIYAMA

IPC: H01L29/66 ,  G11C16/04

Abstract: A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.

公开(公告)号：US20210296354A1

公开(公告)日：2021-09-23

申请号：US17007818

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Yasuhiro UCHIYAMA

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.

公开(公告)号：US20210082877A1

公开(公告)日：2021-03-18

申请号：US16803228

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro UCHIYAMA

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.