公开(公告)号：US20250006675A1

公开(公告)日：2025-01-02

申请号：US18667435

申请日：2024-05-17

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H01L23/00 ,  H10B80/00

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first metal pad provided on a first surface of the first chip and a first circuit connected to the first metal pad. The second chip has a second surface bonded to the first surface of the first chip. The second chip includes a second metal pad provided on the second surface and bonded to the first metal pad, and a second circuit connected to the second metal pad. The first metal pad has a first recess formed in the first surface, and a first carbon film is provided in the first recess.

公开(公告)号：US20240389328A1

公开(公告)日：2024-11-21

申请号：US18664450

申请日：2024-05-15

Applicant: Kioxia Corporation

Inventor： Kazuma HAYASHI ,  Shinya ARAI ,  Keisuke SUDA ,  Masakazu SAWANO

IPC: H10B43/35 ,  H01L23/528 ,  H10B43/10

Abstract: In general, according to one embodiment, a semiconductor device includes: a plurality of first conductor layers arranged apart from each other in a first direction; a memory pillar extending in the first direction and including a portion crossing a respective one of the first conductor layers, the portion functioning as a memory cell; and a first conductor member surrounding, in a first direction perspective, the first conductor layers and the memory pillar, the first conductor member crossing an extension of at least one of the first conductor layers. The first conductor member includes a first direction first end having, in the first direction perspective, a dent and rise profile in a longitudinal direction of the first conductor member.

公开(公告)号：US20230129339A1

公开(公告)日：2023-04-27

申请号：US18145979

申请日：2022-12-23

Applicant: Kioxia Corporation

Inventor： Takahiro TOMIMATSU ,  Shinya ARAI

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a first substrate; a first insulating film provided on the first substrate; a first plug provided in the first insulating film; a second substrate provided on the first insulating film; and a first wiring including a first portion and a second portion. The first portion is provided in the second substrate and coupled to the first plug, and the second portion is provided on the second substrate and coupled to a bonding pad.

公开(公告)号：US20220399312A1

公开(公告)日：2022-12-15

申请号：US17891659

申请日：2022-08-19

Applicant: Kioxia Corporation

Inventor： Shinya ARAI

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/50 ,  H01L23/544

Abstract: A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

公开(公告)号：US20230307387A1

公开(公告)日：2023-09-28

申请号：US17822248

申请日：2022-08-25

Applicant: Kioxia Corporation

Inventor： Ayako KAWANISHI ,  Shinya ARAI

IPC: H01L23/60 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/30205

Abstract: A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.

公开(公告)号：US20230307361A1

公开(公告)日：2023-09-28

申请号：US17901644

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11551

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/11578 ,  H01L27/11551

Abstract: A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

公开(公告)号：US20230017218A1

公开(公告)日：2023-01-19

申请号：US17952718

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/762

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

公开(公告)号：US20220320139A1

公开(公告)日：2022-10-06

申请号：US17848789

申请日：2022-06-24

Applicant: KIOXIA CORPORATION

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

公开(公告)号：US20240397721A1

公开(公告)日：2024-11-28

申请号：US18797474

申请日：2024-08-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20230320107A1

公开(公告)日：2023-10-05

申请号：US18330779

申请日：2023-06-07

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA ,  Akira MINO ,  Masayoshi TAGAMI ,  Shinya ARAI

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  G11C16/0483 ,  G11C16/26 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.