公开(公告)号：US08085570B2

公开(公告)日：2011-12-27

申请号：US12615086

申请日：2009-11-09

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： G11C17/00 ,  G11C17/06 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C17/06

摘要： A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

摘要翻译： 存储器包括提供为沿着字线延伸的导电层，每个存储单元包括具有连接到导电层的阴极的二极管和读取存储在存储单元中的数据的源极线，其中导电层或位线处于 处于待机状态的浮动状态。

公开(公告)号：US07933148B2

公开(公告)日：2011-04-26

申请号：US12562724

申请日：2009-09-18

申请人： Yoshiki Murayama ,  Kouichi Yamada

发明人： Yoshiki Murayama ,  Kouichi Yamada

IPC分类号： G11C11/34

CPC分类号： G11C11/22 ,  G11C13/0004 ,  G11C13/004

摘要： A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

摘要翻译： 提供了能够抑制数据判定精度降低的存储器。 该存储器包括连接到用于保持数据的位线的存储器单元和其基极连接到位线的双极晶体管。 在数据读取中，存储器通过放大与双极晶体管在位线上出现的存储单元的数据相对应的电流来读取数据。

公开(公告)号：US07723723B2

公开(公告)日：2010-05-25

申请号：US11473148

申请日：2006-06-23

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： H01L29/00

CPC分类号： H01L27/1021

摘要： A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

摘要翻译： 可以获得允许减小存储单元大小的存储器。 该存储器包括：形成在半导体衬底的主表面上的第一导电型第一杂质区，用作用于存储单元中包括的二极管的第一电极和字线;多个第二导电型第二杂质区 所述第一杂质区的表面以规定的间隔，各自用作二极管的第二电极，形成在半导体衬底上并连接到第二杂质区的位线和设置在位线上方并连接到第一杂质的线 区域每隔规定间隔。

公开(公告)号：US20090034316A1

公开(公告)日：2009-02-05

申请号：US12183785

申请日：2008-07-31

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： G11C17/00 ,  G11C17/06

CPC分类号： G11C17/06 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206

摘要： A memory includes a plurality of word lines, a plurality of bit lines so arranged as to intersect with the plurality of word lines, a plurality of memory cells arranged on positions where the word lines and the bit lines intersect with each other respectively and selection circuits connected to the bit lines, wherein the current driving ability of the selection circuits is different depending on positions where the bit lines are arranged.

摘要翻译： 存储器包括多个字线，多个位线被布置为与多个字线相交，多个存储单元分别布置在字线和位线分别相交的位置上，选择电路 连接到位线，其中选择电路的当前驱动能力根据位线布置的位置而不同。

公开(公告)号：US20080206946A1

公开(公告)日：2008-08-28

申请号：US12149137

申请日：2008-04-28

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： H01L21/336

CPC分类号： H01L27/11253 ,  G11C11/15 ,  G11C17/06 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11293 ,  H01L27/224 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/91

摘要： A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

摘要翻译： 提供了能够减小存储单元大小的存储器。 该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区， 以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

公开(公告)号：US20060289943A1

公开(公告)日：2006-12-28

申请号：US11473148

申请日：2006-06-23

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： H01L29/76

CPC分类号： H01L27/1021

摘要： A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

摘要翻译： 可以获得允许减小存储单元大小的存储器。 该存储器包括形成在半导体衬底的主表面上的第一导电类型的第一杂质区域，用作用于存储单元中包括的二极管的第一电极和字线，形成在第二导电类型的第二杂质区 所述第一杂质区的表面以规定的间隔，各自用作二极管的第二电极，形成在半导体衬底上并连接到第二杂质区的位线和设置在位线上方并连接到第一杂质的线 区域每隔规定间隔。

公开(公告)号：US20050281606A1

公开(公告)日：2005-12-22

申请号：US10652924

申请日：2003-08-28

申请人： Hiroyuki Koyama ,  Katsumune Hayashi ,  Kouichi Yamada

发明人： Hiroyuki Koyama ,  Katsumune Hayashi ,  Kouichi Yamada

IPC分类号： B26D1/38 ,  B26D7/26 ,  B41J11/00 ,  B41J11/04 ,  B41J11/66 ,  B41J11/70 ,  B41J13/10 ,  B41J15/02 ,  B41J15/04 ,  B41J29/00 ,  B41J29/13 ,  B65H5/38

CPC分类号： B26D1/385 ,  B26D7/2614 ,  B26D2001/0066 ,  B41J11/0045 ,  B41J11/006 ,  B41J11/70 ,  B41J15/042

摘要： A printing section has a platen and a printhead which are oppositely located on both sides of a guide path for guiding the paper. A cutter section has a stationary blade and a movable blade located oppositely to either one of the platen and the printhead on both sides of the guide path. At the cutter section, the paper printed at the printing section is cut by engagement between the stationary blade and the movable blade. Either one of the stationary blade and the movable blade is held on a first unit located on one side of the guide path. On the other hand, either the other of the platen and the printhead and either the other of the stationary blade and the movable blade are held on a second unit which is located on the other side of the guide path. That is, the printing section and the cutter section are constructed by thus connecting the first unit to the second unit assembled as described above. Since the second unit is removably connected to the first unit, such components as the printing section and the cutter section can readily be replaced by detaching the second unit from the first unit.

摘要翻译： 打印部分具有相对地位于用于引导纸张的引导路径两侧的压板和打印头。 切割器部分具有固定刀片和与引导路径两侧的压板和打印头中的任一个相对设置的可动刀片。 在切割器部分，通过固定刀片和可动刀片之间的接合来切割在打印部分上打印的纸张。 固定刀片和可动刀片中的任一个被保持在位于引导路径一侧的第一单元上。 另一方面，压板和打印头中的另一个以及固定刀片和可动刀片中的另一个固定在位于引导路径另一侧的第二单元上。 也就是说，打印部分和切割器部分通过将第一单元连接到如上所述组装的第二单元构成。 由于第二单元可移除地连接到第一单元，因此可以通过将第二单元与第一单元分离来容易地替换打印部分和切割器部分等部件。

公开(公告)号：US20050205943A1

公开(公告)日：2005-09-22

申请号：US11073897

申请日：2005-03-08

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： G11C11/15 ,  G11C17/06 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11253 ,  G11C11/15 ,  G11C17/06 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11293 ,  H01L27/224 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/91

摘要： A memory capable of reducing the memory cell size is provided. This memory comprises a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

摘要翻译： 提供了能够减小存储单元大小的存储器。 该存储器包括形成在半导体衬底的主表面的存储单元阵列区域上的第一导电型第一杂质区，用作用于存储单元中包含的二极管的第一电极和多个第二导电型第二杂质区， 以规定的间隔形成在第一杂质区域的表面上，各自用作二极管的第二电极。

公开(公告)号：US06793424B2

公开(公告)日：2004-09-21

申请号：US10443944

申请日：2003-05-22

申请人： Kouichi Yamada ,  Hiroyuki Koyama ,  Katsumune Hayashi

发明人： Kouichi Yamada ,  Hiroyuki Koyama ,  Katsumune Hayashi

IPC分类号： B41J1170

CPC分类号： B26D1/385 ,  B26D7/2614 ,  B41J11/70 ,  Y10T83/489 ,  Y10T83/7684

摘要： A cutter device comprising a fixed blade and a movable blade is disclosed, the movable blade being opposed to the fixed blade and adapted to be displaced in such a manner that an engaging position thereof with the fixed blade shifts continuously. The cutter device is constructed so that the movable blade can be attached to and detached from a body of the device. Thus, attachment and detachment of the movable blade can be effected without requiring any troublesome work.

公开(公告)号：US06549455B2

公开(公告)日：2003-04-15

申请号：US09985770

申请日：2001-11-06

申请人： Kouichi Yamada

发明人： Kouichi Yamada

IPC分类号： G11C1100

CPC分类号： H01L27/228 ,  G11C11/16

摘要： A magnetic memory device capable of preventing complication of the structure of an amplifier (sense amplifier) and enabling high-speed reading is provided. In this magnetic memory device, a memory cell is formed by a pair of first and second storage elements exhibiting a ferromagnetic tunnel effect and a pair of first and second transistors while an amplifier detects potential difference between a bit line and an inverted bit line connected to the pair of first and second storage elements. Thus, data can be readily read. Further, the value of a small current flowing to the bit line may not be detected dissimilarly to a case of forming the memory cell by a storage element exhibiting a ferromagnetic tunnel effect and a transistor. Consequently, the structure of the amplifier is not complicated. Further, no amplifier having a complicated structure may be employed, whereby high-speed reading is enabled.