公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06458284B1

公开(公告)日：2002-10-01

申请号：US09495306

申请日：2000-02-01

申请人： Keiichiro Kashihara

发明人： Keiichiro Kashihara

IPC分类号： H01L2100

CPC分类号： H01L21/32136 ,  H01L21/32139

摘要： A TiSiN (titanium silicon nitride) film or a multilayered film comprised of a TiSiN film and a TiSi film is used as a hard mask. The TiSiN film (1a) has good adherence to and a high etch selectivity to metal (2), and TiSi is a material having a higher etch selectivity to metal than TiSiN. The use of these materials as an etch mask solves problems with a conventional hard mask such as an SiO2 film. The use of the TiSiN film also as a barrier metal layer (3) allows the process to proceed rapidly in the steps of forming and removing the hard mask and the barrier metal layer. An etching method uses the hard mask made of the material which has good adherence to and a high etch selectivity to an electrode material and which requires the uncomplicated steps of forming and removing the same.

摘要翻译： 使用TiSiN（氮化钛）膜或由TiSiN膜和TiSi膜构成的多层膜作为硬掩模。 TiSiN膜（1a）对金属（2）具有良好的粘附性和高蚀刻选择性，并且TiSi是具有比TiSiN更高的金属蚀刻选择性的材料。 使用这些材料作为蚀刻掩模解决了诸如SiO 2膜的常规硬掩模的问题。 使用TiSiN膜也可以作为阻挡金属层（3），使得该工艺在形成和去除硬掩模和阻挡金属层的步骤中快速进行。 蚀刻方法使用由材料制成的硬掩模，其对电极材料具有良好的粘附性和高蚀刻选择性，并且需要形成和除去电极材料的不复杂步骤。

公开(公告)号：US5534458A

公开(公告)日：1996-07-09

申请号：US442925

申请日：1995-05-17

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US5459345A

公开(公告)日：1995-10-17

申请号：US264092

申请日：1994-06-22

申请人： Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： An object of the invention is to provide a semiconductor device which has a capacitor having good anti-leak characteristics and good breakdown voltage characteristics and is suitable to high integration. Source/drain regions (25) are formed at a surface of a silicon substrate (31). Interlayer insulating films (1) and (3) having contact holes (1a) and (3a), through which a surfaces of the source/drain region is partially exposed, is formed on the surface of silicon substrate (31). Contact holes (1a) and (3a) are filled with plug layer (9a). A capacitor (20) having a highly dielectric film (15) is formed such that it is electrically connected to source/drain region (25) through plug layer (9a). The interlayer insulating film is formed of a two-layer structure including a silicon oxide film (1) and a silicon nitride film (3). Silicon nitride film (3) and plug layer (9a) have the top surfaces flush with each other.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有具有良好的防漏电特性和良好的击穿电压特性的电容器，并且适用于高集成度。 源极/漏极区（25）形成在硅衬底（31）的表面。 在硅衬底（31）的表面上形成具有接触孔（1a）和（3a）的层间绝缘膜（1）和（3），源极/漏极区域的表面部分露出。 接触孔（1a）和（3a）填充有塞层（9a）。 具有高电介质膜（15）的电容器（20）形成为通过插塞层（9a）与源极/漏极区域（25）电连接。 层间绝缘膜由包括氧化硅膜（1）和氮化硅膜（3）的两层结构形成。 氮化硅膜（3）和插塞层（9a）的上表面彼此齐平。