公开(公告)号：US08304914B2

公开(公告)日：2012-11-06

申请号：US12912602

申请日：2010-10-26

申请人： Naofumi Takahata ,  Masahiko Higashi ,  Yukihiro Utsuno

发明人： Naofumi Takahata ,  Masahiko Higashi ,  Yukihiro Utsuno

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11568

摘要： A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.

摘要翻译： 一种制造半导体器件的方法，所述方法包括：在半导体衬底中形成位线; 在所述半导体衬底上形成与所述位线以预定间隔相交的多个字线; 消除多个字线的一部分; 在半导体衬底上形成层间绝缘膜; 以及形成穿过所述层间绝缘膜的金属插塞，并且在所述多个字线的所述部分被去除的区域中耦合到所述位线。

公开(公告)号：US07977189B2

公开(公告)日：2011-07-12

申请号：US12502891

申请日：2009-07-14

申请人： Masahiko Higashi

发明人： Masahiko Higashi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.

摘要翻译： 半导体器件技术领域本发明涉及一种半导体器件，其包括其上形成有源极/漏极扩散区域（14）的半导体衬底（10）和形成在其上的控制栅极（20），在半导体衬底的表面上形成有沟槽（18） （10）并且位于控制栅极（20）下方和源极/漏极扩散区域（14）之间。 凹槽（18）与源极/漏极扩散区域（14）分离，从而增加了有效沟道长度，以保持用于电荷累积的恒定沟道长度，同时能够制造更小的存储单元。 本发明还提供一种半导体器件的制造方法。

公开(公告)号：US20090325354A1

公开(公告)日：2009-12-31

申请号：US12502891

申请日：2009-07-14

申请人： Masahiko Higashi

发明人： Masahiko Higashi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.

摘要翻译： 半导体器件技术领域本发明涉及一种半导体器件，其包括其上形成有源极/漏极扩散区域（14）的半导体衬底（10）和形成在其上的控制栅极（20），在半导体衬底的表面上形成有沟槽（18） （10）并且位于控制栅极（20）下方和源极/漏极扩散区域（14）之间。 凹槽（18）与源极/漏极扩散区域（14）分离，从而增加了有效沟道长度，以保持用于电荷累积的恒定沟道长度，同时能够制造更小的存储单元。 本发明还提供一种半导体器件的制造方法。

公开(公告)号：US07479427B2

公开(公告)日：2009-01-20

申请号：US11237591

申请日：2005-09-27

申请人： Masahiko Higashi ,  Hiroyuki Nansei

发明人： Masahiko Higashi ,  Hiroyuki Nansei

IPC分类号： H01L21/8247

CPC分类号： H01L27/105 ,  H01L21/26586 ,  H01L27/11534 ,  H01L27/11568

摘要： A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.

摘要翻译： 半导体存储器件采用SONOS型存储器架构，并且在其中埋入导电膜的浅沟槽沟槽中包括位线扩散层。 这使得可以在不扩大半导体衬底的主表面上的面积的情况下降低位线扩散层的电阻率，并且制造具有稳定的电特性的半导体存储器件而不扩大单元面积。 位线通过将离子注入到Si 3 N 4的侧壁中而形成。

公开(公告)号：US07253046B2

公开(公告)日：2007-08-07

申请号：US11065305

申请日：2005-02-25

申请人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/8238

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02252 ,  H01L21/28282 ,  H01L21/31155 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.

摘要翻译： 在通过使用具有径向线槽天线的等离子体处理器通过等离子体氮化方法形成的氮化硅膜（22）夹在氧化硅膜（21），（23）上的ONO膜之后，位线扩散层（17） ）通过离子注入形成在存储单元阵列区域（11）中，作为抗蚀剂图案（16）作为掩模，然后通过进一步的离子注入向氮化硅膜（22）提供晶格缺陷。 因此，可以实现在低温条件下形成高质量氮化物膜的高度可靠的半导体存储器件，此外，氮化物膜可以用作具有充分适应于 小型化和高度一体化是最近的需求。

公开(公告)号：US20050212074A1

公开(公告)日：2005-09-29

申请号：US11065307

申请日：2005-02-25

申请人： Kentaro Sera ,  Hiroyuki Nansei ,  Manabu Nakamura ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Kentaro Sera ,  Hiroyuki Nansei ,  Manabu Nakamura ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76235

摘要： A trench (4) is formed in a semiconductor substrate (1), and then a plasma oxynitride film (5) is formed on a side wall surface and a bottom surface of the trench (4) at a temperature of approximately 300° C. to 650° C. At such a temperature, no outward diffusion of impurities from the semiconductor substrate (1) occurs. Therefore, any problems such as formation of a parasitic transistor hardly occur even when ions of impurities are not implanted thereafter. After the plasma oxynitride film (5) is formed, it is thermally oxidized, and a portion where the outermost surface of the semiconductor substrate (1) meets the wall surface of the trench (4) is turned into a curved surface. As a result, the outermost surface of the semiconductor substrate (1) and the wall surface of the trench (4) meet each other while forming a curved surface, and hence a parasitic transistor is hardly formed at this portion. Consequently, formation of a hump is prevented, thereby achieving favorable characteristics.

摘要翻译： 在半导体衬底（1）中形成沟槽（4），然后在约300℃的温度下在沟槽（4）的侧壁表面和底表面上形成等离子体氧氮化物膜（5） 到650℃。在这样的温度下，不会发生杂质从半导体衬底（1）的向外扩散。 因此，即使其后没有植入杂质的离子，也难以形成诸如形成寄生晶体管的问题。 在形成等离子体氮氧化物膜（5）之后，其被热氧化，并且半导体衬底（1）的最外表面与沟槽（4）的壁表面相交的部分变成弯曲表面。 结果，半导体衬底（1）的最外表面和沟槽（4）的壁表面在形成弯曲表面的同时彼此相遇，因此在该部分难以形成寄生晶体管。 因此，防止形成隆起，从而获得有利的特性。

公开(公告)号：US06348427B1

公开(公告)日：2002-02-19

申请号：US09495567

申请日：2000-02-01

申请人： Noriaki Hamada ,  Hideto Yonekura ,  Kenichi Nagae ,  Youji Furukubo ,  Yoshihiro Nakao ,  Masahiko Higashi

发明人： Noriaki Hamada ,  Hideto Yonekura ,  Kenichi Nagae ,  Youji Furukubo ,  Yoshihiro Nakao ,  Masahiko Higashi

IPC分类号： C03C100

CPC分类号： C03C10/0036 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K1/0306 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01005

摘要： A glass ceramic sintered product obtained by sintering a mixture powder containing a BaO-containing glass, metal oxide particles having a coefficient of linear thermal expansion at 40 to 400° C. of not smaller than 6 ppm/°C., and a Zr compound and, particularly, containing the Zr compound in an amount of from 0.1 to 30% by weight calculated as Zr02, and exhibiting a coefficient of linear thermal expansion at 40 to 400° C. of from 8.5 to 18 ppm/°C. The glass ceramic sintered product exhibits excellent resistance against chemicals and does not discolor even when subjected to treatment with an acidic or alkaline solution in the step of plating. A wiring board using the glass ceramic sintered product as an insulating substrate exhibits a coefficient of linear thermal expansion substantially similar to that of an external circuit board, effectively suppressing the occurrence of thermal stress and cracking.

摘要翻译： 将通过烧结含有BaO的玻璃的混合粉末，40〜400℃的线性热膨胀系数的金属氧化物粒子为6ppm /℃以上的玻璃陶瓷烧结体和Zr化合物 特别是含有以ZrO 2计为0.1〜30重量％的Zr化合物，在40〜400℃下的线热膨胀系数为8.5〜18ppm /℃。 玻璃陶瓷烧结产品表现出优异的耐化学性，即使在电镀步骤中用酸性或碱性溶液进行处理也不会变色。 使用玻璃陶瓷烧结体作为绝缘基板的布线基板具有与外部电路基板基本相似的线性热膨胀系数，有效地抑制了热应力和开裂的发生。

公开(公告)号：US08993189B2

公开(公告)日：2015-03-31

申请号：US13146391

申请日：2010-01-25

申请人： Masahiko Higashi ,  Tetsurou Fujimoto ,  Norimitsu Fukami ,  Kenji Shimazu

发明人： Masahiko Higashi ,  Tetsurou Fujimoto ,  Norimitsu Fukami ,  Kenji Shimazu

IPC分类号： H01M8/10 ,  H01M8/02 ,  H01M2/32 ,  H01M2/24 ,  H01M2/22 ,  H01M2/20 ,  H01M8/24 ,  H01M8/12

CPC分类号： H01M8/0206 ,  H01M8/0228 ,  H01M8/2475 ,  H01M8/249 ,  H01M2008/1293 ,  Y02E60/50 ,  Y02E60/525

摘要： A heat-resistant alloy capable of effectively suppressing diffusion of Cr, as well as an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device are provided. A heat-resistant alloy includes a Cr-containing alloy, and a Cr-diffusion suppression layer located on at least a part of a surface of the Cr-containing alloy, the Cr-diffusion suppression layer being made by laminating a first layer that contains a Zn-containing oxide and a second layer that does not contain ZnO but contains an (La, Sr)MnO3-based perovskite oxide in that order, so that it is possible to effectively suppress diffusion of Cr. By using the heat-resistant alloy for an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device each having improved reliability can be obtained.

摘要翻译： 提供能够有效抑制Cr扩散的耐热合金，以及燃料电池用合金部件，燃料电池堆装置，燃料电池模块和燃料电池装置。 耐热合金包括含Cr合金和位于含Cr合金的表面的至少一部分上的Cr扩散抑制层，Cr扩散抑制层通过层压含有 含有Zn的氧化物和不含ZnO但含有（La，Sr）MnO 3系钙钛矿型氧化物的第二层，因此能够有效地抑制Cr的扩散。 通过使用用于燃料电池用合金部件的耐热合金，可以获得具有提高的可靠性的燃料电池堆装置，燃料电池模块和燃料电池装置。

公开(公告)号：US20110281194A1

公开(公告)日：2011-11-17

申请号：US13146391

申请日：2010-01-25

申请人： Masahiko Higashi ,  Tetsurou Fujimoto ,  Norimitsu Fukami ,  Kenji Shimazu

发明人： Masahiko Higashi ,  Tetsurou Fujimoto ,  Norimitsu Fukami ,  Kenji Shimazu

IPC分类号： H01M4/64 ,  H01M8/24 ,  B32B15/04 ,  H01M8/04

CPC分类号： H01M8/0206 ,  H01M8/0228 ,  H01M8/2475 ,  H01M8/249 ,  H01M2008/1293 ,  Y02E60/50 ,  Y02E60/525

摘要： A heat-resistant alloy capable of effectively suppressing diffusion of Cr, as well as an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device are provided. A heat-resistant alloy includes a Cr-containing alloy, and a Cr-diffusion suppression layer located on at least a part of a surface of the Cr-containing alloy, the Cr-diffusion suppression layer being made by laminating a first layer that contains a Zn-containing oxide and a second layer that does not contain ZnO but contains an (La, Sr)MnO3-based perovskite oxide in that order, so that it is possible to effectively suppress diffusion of Cr. By using the heat-resistant alloy for an alloy member for a fuel cell, a fuel cell stack device, a fuel cell module and a fuel cell device each having improved reliability can be obtained.

摘要翻译： 提供能够有效抑制Cr扩散的耐热合金，以及燃料电池用合金部件，燃料电池堆装置，燃料电池模块和燃料电池装置。 耐热合金包括含Cr合金和位于含Cr合金的表面的至少一部分上的Cr扩散抑制层，Cr扩散抑制层通过层压含有 含有Zn的氧化物和不含ZnO但含有（La，Sr）MnO 3系钙钛矿型氧化物的第二层，因此能够有效地抑制Cr的扩散。 通过使用用于燃料电池用合金部件的耐热合金，可以获得具有提高的可靠性的燃料电池堆装置，燃料电池模块和燃料电池装置。

公开(公告)号：US07910980B2

公开(公告)日：2011-03-22

申请号：US12235321

申请日：2008-09-22

申请人： Hiroshi Murai ,  Masahiko Higashi

发明人： Hiroshi Murai ,  Masahiko Higashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/11565

摘要： The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括设置在半导体衬底中的位线，设置在半导体衬底上的位线之间的第一ONO和设置在每个位线上的第二ONO膜。 第一ONO膜中的第一氮化硅膜的膜厚度大于第二ONO膜中的第二氮化硅膜的膜厚度。