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228 条记录 (耗时 0.032 秒)

    Motion vector encoding device and decoding device
    36.
    发明授权
    Motion vector encoding device and decoding device 有权
    运动矢量编码装置和解码装置

    公开(公告)号：US08184708B2

    公开(公告)日：2012-05-22

    申请号：US12470095

    申请日：2009-05-21

    申请人： Akira Nakagawa ,  Taizo Anan ,  Eishi Morimatsu ,  Takashi Itoh

    发明人： Akira Nakagawa ,  Taizo Anan ,  Eishi Morimatsu ,  Takashi Itoh

    IPC分类号： H04N7/12

    CPC分类号： H04N19/00587 ,  H04N19/105 ,  H04N19/12 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/176 ,  H04N19/51 ,  H04N19/513 ,  H04N19/52 ,  H04N19/61

    摘要： A prediction error generating unit generates a predictive vector from the motion vectors of a plurality of adjacent blocks, and obtains a difference from a target vector. A plurality of variable-length coding units respectively encode the output of the prediction error generating unit with different encoding methods. A determining unit estimates the accuracy of the predictive vector generated by the prediction error generating unit based on the degrees of non-uniformity of the motion vectors of the plurality of adjacent blocks. A selecting unit selects one of the encoding results obtained by the plurality of variable-length coding units.

    摘要翻译： 预测误差生成单元从多个相邻块的运动矢量生成预测矢量，并且从目标矢量获得差。 多个可变长度编码单元分别以不同的编码方式编码预测误差生成单元的输出。 确定单元基于多个相邻块的运动矢量的不均匀度来估计由预测误差生成单元生成的预测矢量的精度。 选择单元选择由多个可变长度编码单元获得的编码结果之一。

    Manufacturing method for semiconductor chips, and semiconductor chip
    37.
    发明授权
    Manufacturing method for semiconductor chips, and semiconductor chip 有权
    半导体芯片的制造方法和半导体芯片

    公开(公告)号：US08012805B2

    公开(公告)日：2011-09-06

    申请号：US11918432

    申请日：2006-04-11

    申请人： Kiyoshi Arita ,  Akira Nakagawa

    发明人： Kiyoshi Arita ,  Akira Nakagawa

    IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301

    CPC分类号： H01L21/6835 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/78 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2924/30105

    摘要： In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing regions is placed thereby exposing the insulating film from etching bottom portions by removing portions that correspond to the dividing regions and subsequently continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma thereby removing corner portions put in contact with the insulating film in the device-formation-regions, isotropic etching is performed on the semiconductor wafer at any timing.

    摘要翻译： 在用于在半导体晶片的第二表面上进行等离子体蚀刻的制造方法中，所述半导体晶片具有绝缘膜放置在分割区域中的第一表面和与第一表面相反的第二表面，并且在其上形成用于限定分割的掩模 放置区域，通过除去与分割区域相对应的部分，然后在绝缘膜的暴露表面由于电子束中的离子而被充电的状态下连续进行等离子体蚀刻而使绝缘膜暴露于蚀刻底部 等离子体，从而去除与器件形成区域中的绝缘膜接触的拐角部分，在任何时刻对半导体晶片进行各向同性蚀刻。

    Method for dividing semiconductor wafer and manufacturing method for semiconductor devices
    38.
    发明授权
    Method for dividing semiconductor wafer and manufacturing method for semiconductor devices 有权
    半导体晶片分割方法及其制造方法

    公开(公告)号：US07927973B2

    公开(公告)日：2011-04-19

    申请号：US11663543

    申请日：2005-10-04

    申请人： Hiroshi Haji ,  Kiyoshi Arita ,  Akira Nakagawa ,  Kazuhiro Noda

    发明人： Hiroshi Haji ,  Kiyoshi Arita ,  Akira Nakagawa ,  Kazuhiro Noda

    IPC分类号： H01L21/78 ,  H01L21/308

    CPC分类号： H01L21/78

    摘要： In a semiconductor wafer including a plurality of imaginary-divided-regions which are partitioned by imaginary-dividing-lines that are respectively arranged in a grid-like arrangement on the semiconductor wafer and a circumferential line that is the outer periphery outline of the semiconductor wafer, a mask is placed so as to expose an entirety of surfaces of the wafer corresponding to respective removal-regions. The removal-regions are regions in approximately triangular form partitioned by the circumferential line of the wafer and the imaginary-dividing-lines. Then, plasma etching is performed on a mask placement-side surface of the wafer, by which the semiconductor wafer is divided into the individual semiconductor devices along dividing lines while portions corresponding to the removal-regions of the wafer are removed.

    摘要翻译： 在半导体晶片中，具有分别由在半导体晶片上排列成格子状的虚拟分割线分隔的多个虚分割区域和作为半导体晶片的外周轮廓的周向线 放置掩模以使与相应的移除区域对应的晶片的整个表面露出。 去除区域是由晶片的圆周线和假想分界线分隔的大致三角形的区域。 然后，在晶片的掩模放置侧表面上执行等离子体蚀刻，通过该等离子体蚀刻，半导体晶片沿着划分线被划分成各个半导体器件，同时去除与晶片的去除区域相对应的部分。