公开(公告)号：US20120279548A1

公开(公告)日：2012-11-08

申请号：US13500616

申请日：2010-05-17

申请人： Markus Münch ,  Stefan Tegen

发明人： Markus Münch ,  Stefan Tegen

IPC分类号： H01L31/05 ,  H01L31/18

CPC分类号： H01L31/0508 ,  H01L31/046 ,  H01L31/0465 ,  Y02E10/50

摘要： The invention relates to an arrangement and circuit, and to a method for interconnecting flat rigid or flexible solar cells, the photoelectrical active layers thereof being applied to an insulating substrate material. The aim of the invention is provide a novel arrangement and circuit and an associated method for interconnecting flat solar cells, reducing the risk of short circuit and the inactive surface area in the matrix composite of the solar module and selectively allowing simple interconnection, both as a parallel circuit and as a series circuit in production. The solar cells (1) in the arrangement and circuit of flat rigid or flexible solar cells are disposed overlapping in the contact area to one or more adjacent solar cells (1). Said solar cells (1) are interconnected to each other directly once or a plurality of times in a novel manner, having a contact material (10) at the overlapping area to each other, used in contact material (10) or switching points (22).

摘要翻译： 本发明涉及一种布置和电路以及将平坦的刚性或柔性太阳能电池互连的方法，其光电活性层被施加到绝缘衬底材料上。 本发明的目的是提供一种用于互连扁平太阳能电池的新型布置和电路以及相关联的方法，降低了太阳能模块的矩阵复合材料中的短路风险和非活动表面积，并且选择性地允许简单的互连 并联电路和串联电路在生产中。 扁平刚性或柔性太阳能电池的布置和电路中的太阳能电池（1）在接触区域中重叠设置在一个或多个相邻的太阳能电池（1）上。 所述太阳能电池（1）在接触材料（10）或切换点（22）中以新颖的方式直接相互连接一次或多次，其中在触点材料（10）处于彼此重叠的区域 ）。

公开(公告)号：US20070020905A1

公开(公告)日：2007-01-25

申请号：US11184074

申请日：2005-07-19

申请人： Stefan Tegen

发明人： Stefan Tegen

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76802

摘要： In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface and the silicon oxide and an opening is produced in the layer, said opening abutting on the silicon oxide. The selectively grown silicon oxide is removed and the opening is filled with electrically conductive material, whereby the electrically conductive material forms the contact.

摘要翻译： 在制造与导电硅结构电接触的接触的方法中，提供具有表面的基板，所述基板在表面具有硅结构。 硅氧化物选择性地生长在硅结构的至少一部分上。 在该表面上产生一层，并且在该层中产生氧化硅和开口，所述开口邻接在氧化硅上。 去除选择性生长的氧化硅并且用导电材料填充开口，由此导电材料形成接触。

公开(公告)号：US20050056615A1

公开(公告)日：2005-03-17

申请号：US10911294

申请日：2004-08-04

申请人： Peter Moll ,  Stefan Tegen

发明人： Peter Moll ,  Stefan Tegen

IPC分类号： C23F1/00 ,  C23F4/00 ,  H01L21/311

CPC分类号： H01L21/31122

摘要： This invention relates to a method for the selective and directed plasma etching of aluminum oxide, in which a mixture having the following constituents is used for etching: a. a polymerizing gas comprising at least partially unsaturated, perfluorinated hydrocarbon compounds; b. optionally a compound having the formula CHxFy, where x=1-3 and y=4-x; c. oxygen; and d. a suitable carrier gas; and this mixture as a plasma, is brought into contact with the aluminum oxide to be etched.

摘要翻译： 本发明涉及一种用于氧化铝选择性和定向等离子体蚀刻的方法，其中具有以下成分的混合物用于蚀刻：a。 包含至少部分不饱和的全氟化烃化合物的聚合气体; b。 任选地具有式CH x F y的化合物，其中x = 1-3和y = 4-x; C。 氧; 和d。 合适的载气; 并将作为等离子体的混合物与待蚀刻的氧化铝接触。

公开(公告)号：US07456086B2

公开(公告)日：2008-11-25

申请号：US11395111

申请日：2006-03-31

申请人： Stefan Tegen

发明人： Stefan Tegen

IPC分类号： H01L21/22

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31625 ,  H01L27/10852

摘要： A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in a dry-etching step and the aspect ratio of the openings is reduced by increasing the basic surface area of the openings using a subsequent wet-chemical etching step.

摘要翻译： 公开了一种制造具有低纵横比的开口的绝缘结构的方法。 在一个实施例中，掺杂剂以从预处理的半导体表面垂直方向平均增加或减小的浓度引入绝缘结构中，开口形成在干蚀刻步骤中，并且开口的纵横比 通过使用随后的湿化学蚀刻步骤增加开口的基本表面积来减少。

公开(公告)号：US20060281246A1

公开(公告)日：2006-12-14

申请号：US11395111

申请日：2006-03-31

申请人： Stefan Tegen

发明人： Stefan Tegen

IPC分类号： H01L21/8238

CPC分类号： H01L21/31111 ,  H01L21/31116 ,  H01L21/31625 ,  H01L27/10852

摘要： A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in a dry-etching step and the aspect ratio of the openings is reduced by increasing the basic surface area of the openings using a subsequent wet-chemical etching step.

摘要翻译： 公开了一种制造具有低纵横比的开口的绝缘结构的方法。 在一个实施例中，掺杂剂以从预处理的半导体表面垂直方向平均增加或减小的浓度引入绝缘结构中，开口形成在干蚀刻步骤中，并且开口的纵横比 通过使用随后的湿化学蚀刻步骤增加开口的基本表面积来减少。

公开(公告)号：US20080061320A1

公开(公告)日：2008-03-13

申请号：US11851510

申请日：2007-09-07

申请人： Johannes von Kluge ,  Stefan Tegen

发明人： Johannes von Kluge ,  Stefan Tegen

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.

摘要翻译： 集成电路的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域以及被配置为控制在沟道中流动的电流的栅电极。 栅电极设置在栅极沟槽中，该沟槽限定在半导体衬底的顶表面中。 第一和第二源极/漏极区域至少延伸到深度d 1，其中从衬底的顶表面测量深度d 1。 栅电极的顶表面设置在半导体衬底的顶表面之下，距离顶表面的距离小于深度d 1。

公开(公告)号：US07291532B2

公开(公告)日：2007-11-06

申请号：US11184074

申请日：2005-07-19

申请人： Stefan Tegen

发明人： Stefan Tegen

IPC分类号： H01L21/8242

CPC分类号： H01L21/76802

摘要： In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface and the silicon oxide and an opening is produced in the layer, the opening abutting on the silicon oxide. The selectively grown silicon oxide is removed and the opening is filled with electrically conductive material, whereby the electrically conductive material forms the contact.

摘要翻译： 在制造与导电硅结构电接触的接触的方法中，提供具有表面的基板，所述基板在表面具有硅结构。 硅氧化物选择性地生长在硅结构的至少一部分上。 在该表面上产生一层，并且在该层中产生一个开口，该开口邻接在氧化硅上。 去除选择性生长的氧化硅并且用导电材料填充开口，由此导电材料形成接触。

公开(公告)号：US07763514B2

公开(公告)日：2010-07-27

申请号：US11851510

申请日：2007-09-07

申请人： Johannes von Kluge ,  Stefan Tegen

发明人： Johannes von Kluge ,  Stefan Tegen

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.

摘要翻译： 集成电路的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域以及被配置为控制在沟道中流动的电流的栅电极。 栅电极设置在栅极沟槽中，该沟槽限定在半导体衬底的顶表面中。 第一和第二源极/漏极区域至少延伸到深度d1，其中从衬底的顶表面测量深度d1。 栅电极的顶表面设置在半导体衬底的顶表面之下，距离顶表面的距离小于深度d1。