公开(公告)号：US6031788A

公开(公告)日：2000-02-29

申请号：US207335

申请日：1998-12-08

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G06F1/04 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.

摘要翻译： 当半导体集成电路处于有功掉电状态时，半导体集成电路适于使外部提供给半导体集成电路的外部时钟无效。 半导体集成电路包括延迟锁定环DLL电路，其输出与外部时钟同步的内部时钟。 锁存电路保持与DLL电路的内部时钟输出同步的控制信号。 内部电路基于从锁存电路提供的控制信号执行预定处理。

公开(公告)号：US07898890B2

公开(公告)日：2011-03-01

申请号：US12145889

申请日：2008-06-25

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061

摘要： An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided.

摘要翻译： 一种振荡装置，包括：根据使能信号产生振荡信号的振荡器; 计数振荡信号的振荡次数的计数器，并能够以由第一信号指示的振荡次数进行复位; 并且提供比较计数的振荡数和参考数的比较器。

公开(公告)号：US07626881B2

公开(公告)日：2009-12-01

申请号：US11889672

申请日：2007-08-15

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C17/165 ,  G11C17/18

摘要： A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.

摘要翻译： 一种能够减少反熔丝写入电压产生电路的电路规模的半导体存储器件。 半导体存储器件具有第一内部电源产生电路，其升高外部电源电压以产生第一内部电源，提供第一内部电源的存储器芯，用于写入预定信息的反熔丝存储器，以及 写入电压产生电路，其升高第一内部电源以产生反熔丝写入电压。

公开(公告)号：US07221574B2

公开(公告)日：2007-05-22

申请号：US11103551

申请日：2005-04-12

申请人： Hiroyoshi Tomita ,  Toshiya Uchida

发明人： Hiroyoshi Tomita ,  Toshiya Uchida

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4065

摘要： A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.

摘要翻译： 半导体存储装置具有存储数据的存储单元（501,502） 连接到存储单元的位线（BL 1，BL 2），允许数据输入或输出到存储单元; 连接到所述位线的读出放大器（506a），放大位线上的数据; 以及开关晶体管（505a），连接或断开与连接到读出放大器的位线连接到存储单元的位线。 开关晶体管在第一存储器单元存取操作和第二存储单元存取操作中的操作方式不同。

公开(公告)号：US06667933B2

公开(公告)日：2003-12-23

申请号：US09970657

申请日：2001-10-05

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/406

摘要： When a plurality of commands are received in succession to read/write data from/to memory cells in accordance with the combination of these commands, a word line for controlling the transfer switches of the memory cells are activated after the reception of one of the commands excluding the first command. This allows control circuits for activating the word lines to be operated at a lower frequency than heretofore, with a reduction in power consumption. Moreover, the word lines are activated based on an address signal that is supplied along with the first command as well as a part of an address signal supplied along with one of the commands excluding the first command. Consequently, the memory region to be selected by these address signals can be smaller, with a reduction in power consumption.

公开(公告)号：US06549047B2

公开(公告)日：2003-04-15

申请号：US09945618

申请日：2001-09-05

申请人： Masafumi Yamazaki ,  Hiroyoshi Tomita

发明人： Masafumi Yamazaki ,  Hiroyoshi Tomita

IPC分类号： H03L706

CPC分类号： H03K5/133 ,  H03K5/131 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

公开(公告)号：US06460110B2

公开(公告)日：2002-10-01

申请号：US09017702

申请日：1998-02-05

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C29/812 ,  G11C29/816

摘要： The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

摘要翻译： 本发明涉及具有预取结构的半导体存储器。 在这种存储器中，奇数地址单元阵列具有奇数地址冗余单元阵列，并且均匀地址单元阵列具有偶数地址冗余单元阵列，首先，本发明包括冗余存储器，其存储奇数冗余 地址和偶数冗余地址，以及奇数和偶数选择数据。 由于冗余存储器在奇数侧和偶数侧灵活地使用，所以即使在减少冗余存储器容量时也可以保持高的释放概率。

公开(公告)号：US06426909B1

公开(公告)日：2002-07-30

申请号：US09924779

申请日：2001-08-09

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C11/406

摘要： The refresh circuit generates a refresh request for refreshing memory cells at a predetermined interval. The refresh counter generates a refresh address. The holding circuit respectively holds information as to the completion/incompletion of refresh of the memory cells in each of the banks, the memory cells being designated by the refresh address. The refresh control circuit refreshes bank(s) yet to be refreshed among the banks not in operation upon the occurrence of the refresh request, based on the information held in the holding circuit. That is, under a single refresh address, banks yet to be refreshed are successively refreshed every time refresh request occurs. The refresh operations are performed on banks that are not in operation. Therefore, the refresh operations can be performed without being recognized from exterior. That is, the semiconductor memory having a plurality of banks can perform the refresh of memory cells internally and automatically.

摘要翻译： 刷新电路以预定间隔产生用于刷新存储器单元的刷新请求。 刷新计数器生成刷新地址。 保持电路分别保存关于每个存储体中的存储单元的刷新的完成/不完全的信息，存储单元由刷新地址指定。 基于保持电路中保存的信息，刷新控制电路刷新在刷新请求发生之后不工作的存储体中要刷新的存储体。 也就是说，在单个刷新地址下，每次刷新请求发生时，银行尚未刷新。 刷新操作在没有运行的银行上执行。 因此，可以在不从外部识别的情况下执行刷新操作。 也就是说，具有多个存储体的半导体存储器可以在内部和自动地执行存储器单元的刷新。

公开(公告)号：US06376869B1

公开(公告)日：2002-04-23

申请号：US09385013

申请日：1999-08-27

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H01L2972

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1078

摘要： A semiconductor device includes a first terminal for inputting and outputting data and a second terminal for inputting control data in synchronization with a strobe signal. The semiconductor device includes an equivalent circuit which is provided in the second terminal. Further, the equivalent circuit has a capacitance which is equivalent to that in an output circuit which is provided in the first terminal.

摘要翻译： 半导体器件包括用于输入和输出数据的第一端子和用于与选通信号同步地输入控制数据的第二端子。 半导体器件包括设置在第二端子中的等效电路。 此外，等效电路具有与设置在第一端子中的输出电路中的电容相当的电容。

公开(公告)号：US06369627B1

公开(公告)日：2002-04-09

申请号：US09604247

申请日：2000-06-27

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H03L706

CPC分类号： G11C7/22 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0814

摘要： A delay circuit including a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators generates a clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. The subsequent interpolators operate as delay stages, thereby generating a delayed clock signal delaying from the reference clock signal by a predetermined time. It is possible to make smaller the minimum unit of a delay adjustment to the delayed clock signal by using the interpolators. A semiconductor integrated circuit including the delay circuit supplies ratio information to the phase adjustment circuits based on the result of comparing the phase of the reference clock signal with the phase of the delayed clock signal from a phase comparator and makes the phase of the delayed clock signal coincide with the phase of the reference clock signal. As a result, the phase adjustment can be made with reliability even when a reference clock signal of higher frequency is supplied.

摘要翻译： 包括级联连接的多个内插器的延迟电路。 每个内插器接收从前一个插值器输出的参考时钟信号和时钟信号。 其中一个内插器产生一个时钟信号，该时钟信号的过渡沿位于参考时钟信号的过渡沿和时钟信号的过渡沿之间。 随后的内插器作为延迟级操作，由此产生延迟的时钟信号从参考时钟信号延迟预定时间。 通过使用内插器，可以使延迟时钟信号的延迟调整的最小单位更小。 包括延迟电路的半导体集成电路基于将参考时钟信号的相位与来自相位比较器的延迟时钟信号的相位进行比较的结果向相位调整电路提供比率信息，并使延迟的时钟信号的相位 与参考时钟信号的相位一致。 结果，即使提供较高频率的参考时钟信号，也可以进行相位调整。