公开(公告)号：US20090027074A1

公开(公告)日：2009-01-29

申请号：US11829104

申请日：2007-07-27

Applicant: Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

Inventor： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

IPC: G01R31/02 ,  H01L21/66 ,  H01L23/58

CPC classification number: G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

Abstract translation: 本发明公开了一种晶圆级测试结构和测试方法; 其中，在晶片上形成加热板，用于加热待加热板上方或附近的待测试结构。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

公开(公告)号：US06500389B1

公开(公告)日：2002-12-31

申请号：US09561117

申请日：2000-04-28

Applicant: Hsiao-Pang Chou ,  Kuan-Cheng Su

Inventor： Hsiao-Pang Chou ,  Kuan-Cheng Su

IPC: G01N3096

CPC classification number: H01J37/32211 ,  H01J37/32935

Abstract: A plasma arcing sensor is used to increase the frequency of plasma arcing by way of neutralization of positive charges and negative charges. When the plasma arcing can be predicted, the process parameters to prevent from the plasma arcing can be carried out. The plasma arcing sensor comprises a top conductive layer formed over a substrate. A conductive layer is disposed between the top conductive layer and the wafer where the conductive layer and the top conductive layer are electrically isolated with dielectrics.

Abstract translation: 等离子体电弧传感器用于通过中和正电荷和负电荷来增加等离子体电弧的频率。 当可以预测等离子体电弧时，可以进行防止等离子体电弧放电的工艺参数。 等离子体电弧传感器包括在衬底上形成的顶部导电层。 导电层设置在导电层和晶片之间，其中导电层和顶部导电层与电介质电隔离。

公开(公告)号：US5918127A

公开(公告)日：1999-06-29

申请号：US650350

申请日：1996-05-20

Applicant: Chen-Wei Lee ,  Kuan-Cheng Su

Inventor： Chen-Wei Lee ,  Kuan-Cheng Su

IPC: H01L21/8246 ,  H01L27/02 ,  H01L27/112

CPC classification number: H01L27/0266 ,  H01L27/112

Abstract: A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor. The breakdown voltage controlling areas are heavily doped, thereby reducing the breakdown voltage at the junction between the drain and the p-well in the n-type CMOS transistor. This enhances the ESD protection capability of the integrated circuit.

Abstract translation: 提高ESD掩模编程的集成电路中提供的ESD保护装置的ESD（静电放电）保护能力的半导体制造方法允许掩模编程的ROM小型化，同时仍然提供足够的ESD保护能力， 允许以较小的尺寸制造掩模编程的ROM，同时为内部电路提供足够的ESD保护能力。 首先，制备用于ROM的离子注入工艺的掩模。 该掩模附加地具有用于限定ESD保护装置中的击穿电压控制区域的多个条带。 然后，通过掩模进行离子注入工艺，以便在n型CMOS晶体管的漏极下形成击穿电压控制区。 击穿电压控制区域被重掺杂，从而降低n型CMOS晶体管中的漏极和p阱之间的结点处的击穿电压。 这增强了集成电路的ESD保护能力。

公开(公告)号：US5859460A

公开(公告)日：1999-01-12

申请号：US839497

申请日：1997-04-14

Applicant: Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

Inventor： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC: G11C11/56 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/1126 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/112

Abstract: A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls, of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

Abstract translation: 本文公开了三态只读存储器件及其制造方法。 在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。 然后，去除绝缘块的屏蔽层侧壁，并且在其侧壁上形成间隔物。 去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。 通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。 此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

公开(公告)号：US5693551A

公开(公告)日：1997-12-02

申请号：US530575

申请日：1995-09-19

Applicant: Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

Inventor： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC: G11C11/56 ,  H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/1126 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/112

Abstract: A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

Abstract translation: 本文公开了三态只读存储器件及其制造方法。 在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。 然后去除屏蔽层，揭示绝缘块的侧壁，并在其侧壁上形成间隔物。 去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。 通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。 此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

公开(公告)号：US5668030A

公开(公告)日：1997-09-16

申请号：US524549

申请日：1995-09-07

Applicant: Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

Inventor： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC: H01L21/8246 ,  H01L23/544

CPC classification number: H01L27/1126 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

Abstract: A process for fabricating identification alphanumeric code markings on the substrate of mask ROM devices is disclosed. The fabrication process comprises first forming a deposited layer on the substrate of the mask ROM device. A photoresist layer is then formed on the deposited layer. A photomask layer by is then shaped by forming a pattern on the photoresist layer that reveals the channel regions of the memory cell transistors to be programmed into the blocking state, as well as reveals the graphical pattern of the alphanumeric code marking. An etching procedure then removes the portion of the deposited layer revealing the graphical pattern of the alphanumeric code markings. The photomask layer is then removed. A code implantation procedure may precede or follow the etching procedure to facilitate the programming of the memory cells of the mask ROM device.

Abstract translation: 公开了一种用于在掩模ROM器件的衬底上制造识别字母数字代码标记的过程。 制造工艺包括首先在掩模ROM器件的衬底上形成沉积层。 然后在沉积层上形成光致抗蚀剂层。 然后通过在光致抗蚀剂层上形成图案来形成光掩模层，该图案将存储单元晶体管的通道区域显示为被编程成阻塞状态，以及揭示字母数字代码标记的图形图案。 然后，蚀刻过程去除沉积层的部分，露出字母数字代码标记的图形图案。 然后去除光掩模层。 代码注入过程可以在蚀刻过程之前或之后，以便于掩模ROM器件的存储器单元的编程。

公开(公告)号：US5536669A

公开(公告)日：1996-07-16

申请号：US507698

申请日：1995-07-26

Applicant: Kuan-Cheng Su ,  Yi-Chung Sheng ,  Chen-Hui Chung

Inventor： Kuan-Cheng Su ,  Yi-Chung Sheng ,  Chen-Hui Chung

IPC: H01L21/8246

CPC classification number: H01L27/11253

Abstract: A method for fabricating ROM devices with self-aligned code implants comprises the steps of: forming an oxide layer over a silicon substrate; forming a plurality of deposition selecting strips over the oxide layer; forming a dielectric between the plurality of deposition selecting strips to thereby produce a plurality of dielectric strips; removing the deposition selecting strips; forming a number of code diffusion regions in the silicon substrate; and forming a plurality of word lines between the plurality of dielectric strips. Since the code diffusion regions are formed by implanting ions through the dielectric strips, the shielding of the dielectric strips can prevent the outspreading of impurities due to code mask mis-alignment. Therefore, the positions of code diffusion regions can be well controlled beneath the word lines.

Abstract translation: 用于制造具有自对准代码注入的ROM器件的方法包括以下步骤：在硅衬底上形成氧化物层; 在所述氧化物层上形成多个沉积选择条; 在所述多个沉积选择条之间形成电介质，从而产生多个介质条; 去除沉积选择条; 在硅衬底中形成多个代码扩散区域; 以及在所述多个介质条之间形成多个字线。 由于通过将介质条注入离子形成代码扩散区，所以介质条的屏蔽可以防止由于码屏错误对准而导致的杂质扩展。 因此，代码扩散区域的位置可以很好地控制在字线之下。

公开(公告)号：US5429974A

公开(公告)日：1995-07-04

申请号：US139854

申请日：1993-10-22

Applicant: Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract translation: 具有单元阵列的ROM器件具有形成在衬底中的导体。 形成绝缘体，平行导体与线区域正交形成，薄至约2000安。 在导体上形成厚度约为3000或更小的玻璃绝缘体被回流。 形成玻璃绝缘体上的触点和金属层。 抗蚀剂被图案化并用于蚀刻金属中的抗蚀剂图案。 在还原气体气氛中，通过在小于或等于约520℃退火器件使杂质离子激活之前，用厚度约为1000的层去除第二抗蚀剂和器件钝化。 抗蚀剂除去后，形成第二抗蚀剂并用定制的编码图案曝光以形成掩模。 离子以约1E14和3E14原子/ cm2的剂量注入到基底中，其能量小于或等于200keV，通过绝缘体中的开口与导体相邻。