公开(公告)号：US20110205822A1

公开(公告)日：2011-08-25

申请号：US13006832

申请日：2011-01-14

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： G11C7/06 ,  G01R19/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

公开(公告)号：US20100195414A1

公开(公告)日：2010-08-05

申请号：US12691910

申请日：2010-01-22

申请人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

发明人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

IPC分类号： G11C7/06 ,  G11C7/02 ,  G11C5/14 ,  H03K5/153 ,  G05F1/10

CPC分类号： G11C7/04 ,  G01R19/16552 ,  G11C5/147 ,  H03K5/2481

摘要： A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

摘要翻译： 提供了一种电平检测器，包括电平检测器的内部电压发生器和包括内部电压发生器的半导体存储器件。 内部电压发生器包括电平检测器，其将与温度变化的阈值电压与内部电压进行比较以输出比较电压;以及内部电压驱动器，其响应于比较电压调节外部电源电压并且输出内部电压 。

公开(公告)号：US20100097870A1

公开(公告)日：2010-04-22

申请号：US12580585

申请日：2009-10-16

申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

公开(公告)号：US20090225622A1

公开(公告)日：2009-09-10

申请号：US12430163

申请日：2009-04-27

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US07580319B2

公开(公告)日：2009-08-25

申请号：US11715478

申请日：2007-03-08

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096

摘要： An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.

摘要翻译： 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。

公开(公告)号：US07492288B2

公开(公告)日：2009-02-17

申请号：US11693264

申请日：2007-03-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US07408817B2

公开(公告)日：2008-08-05

申请号：US11453518

申请日：2006-06-15

申请人： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

发明人： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

IPC分类号： G11C5/14

CPC分类号： G11C5/145

摘要： A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

摘要翻译： 一种用于半导体存储器件的电压产生电路。 电压产生电路包括用于升高电源电压的多升压单元，连接到多升压单元的最终升压节点的输出晶体管和输出节点，以及与最终的电连接电连接的电荷共享元件 所述传输晶体管的升压节点和栅极节点在所述周期的至少一部分期间被使能，所述多个升压单元对所述电源电压进行升压，并且在所述最终升压节点和所述转移的所述栅极节点之间执行电荷共享 晶体管。

公开(公告)号：US20070211556A1

公开(公告)日：2007-09-13

申请号：US11715478

申请日：2007-03-08

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096

摘要： An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.

摘要翻译： 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。

公开(公告)号：US20070040579A1

公开(公告)日：2007-02-22

申请号：US11503802

申请日：2006-08-14

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： H03K19/0175

CPC分类号： H03K19/01707 ,  H03K19/0013

摘要： A swing limiter comprises: a logic circuit including at least one first pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a second node and receive at least one input signal to generate an output signal, respectively; a second pull-up transistor connected between a first power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the second power voltage in response to a first control voltage; a second pull-down transistor connected between the second node and a second power voltage and causing a voltage of the second node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a second control voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage and generating the first control voltage between the high voltage and the first reference voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage and generating the second control voltage between the low voltage and the second reference voltage.

摘要翻译： 摆动限制器包括：逻辑电路，包括至少一个第一上拉晶体管和至少一个第一下拉晶体管，其串联连接在第一节点和第二节点之间，并且接收至少一个输入信号以产生输出信号 ， 分别; 连接在第一电源电压和第一节点之间的第二上拉晶体管，并且使第一节点的电压具有通过从第二电源电压中减去小于其阈值电压的电压而获得的电压电平 第一控制电压; 连接在第二节点和第二电源电压之间的第二下拉晶体管，并且使得第二节点的电压具有通过将小于其阈值电压的绝对值的电压加到第二电力而获得的电压电平 响应于第二控制电压的电压; 连接在高于第一电源电压的高电压的第一控制电压发生器和低于高电压的第一参考电压并且产生高电压和第一参考电压之间的第一控制电压; 以及第二控制电压发生器，其连接在低于所述第二电力电压的低电压和高于所述低电压的第二参考电压，并且在所述低电压和所述第二参考电压之间产生所述第二控制电压。

公开(公告)号：US06704228B2

公开(公告)日：2004-03-09

申请号：US10160703

申请日：2002-05-30

申请人： Seong-Jin Jang ,  Kyu-Hyoun Kim

发明人： Seong-Jin Jang ,  Kyu-Hyoun Kim

IPC分类号： G11C2900

CPC分类号： G11C29/785

摘要： The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (“post repair”) using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

摘要翻译： 使用采用两种类型的冗余编程的冗余存储器线路控制电路来改进通过用冗余单元替换这些单元来修复存储器阵列中的有缺陷的单元的能力。 当存储器阵列通过例如切割激光熔丝处于晶片状态时，大多数或全部冗余存储器线可被编程。 但是，在使用例如切断电保险丝的命令之后，可以在器件封装（“后修复”）之后至少编写一条存储器线。 优选地，可以在可以使用激光熔丝编程的相同冗余存储器线中选择用于后修复的冗余存储器线。 这样，如果需要，所有冗余存储器线路都可用于激光修复，同时也可以在确定冗余存储器线路无缺陷之后，选择冗余存储器线进行后期修复。 这增加了设备可修复的可能性，并且不会通过预先将其专用于激光或后修复而不必要地浪费冗余的存储器线。