公开(公告)号：US07911862B2

公开(公告)日：2011-03-22

申请号：US12585428

申请日：2009-09-15

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07686009B2

公开(公告)日：2010-03-30

申请号：US11297424

申请日：2005-12-09

申请人： Sung Soo Park ,  Pung Yeun Cho ,  Cheol Jin Kim ,  Kyoung Ho Kim ,  Kil Young Lee ,  Sung Kwang Kim ,  Yu Jeub Ha ,  Yun Ic Hwang ,  Sang Hyun Kang ,  Seok Weon Hong ,  Tae Ho Kim

发明人： Sung Soo Park ,  Pung Yeun Cho ,  Cheol Jin Kim ,  Kyoung Ho Kim ,  Kil Young Lee ,  Sung Kwang Kim ,  Yu Jeub Ha ,  Yun Ic Hwang ,  Sang Hyun Kang ,  Seok Weon Hong ,  Tae Ho Kim

IPC分类号： F23M7/00

CPC分类号： F24C15/04 ,  F24C15/006

摘要： Disclosed herein is an oven that is capable of discharging hot air generated when cooling a door and heat generated in a cooking chamber through the lower end of the door. The oven includes a door having at least two separated air channels. The air channels comprise at least one first air channel to discharge hot air generated when cooling the door through the lower end of the door, and at least one second air channel to introduce air through the lower end of the door such that the door is cooled. In the housing is mounted a circulating fan. Between the circulating fan and the air channels is connected a channel connecting unit. As the circulating fan is rotated, air flows along the second air channel to cool the door. Hot air generated when cooling the door is introduced into the first air channel through the channel connecting unit, and is then discharged out of the oven through the lower end of the door.

摘要翻译： 本文公开了一种烤箱，其能够排出冷却门时产生的热空气和通过门的下端在烹饪室中产生的热量。 烤箱包括具有至少两个分开的空气通道的门。 空气通道包括至少一个第一空气通道，以排出当通过门的下端冷却门时产生的热空气，以及至少一个第二空气通道，以引导空气通过门的下端，使得门被冷却 。 在外壳中安装有循环风扇。 在循环风扇和空气通道之间连接一个通道连接单元。 当循环风扇旋转时，空气沿着第二空气通道流动以冷却门。 冷却门时产生的热空气通过通道连接单元引入第一空气通道，然后通过门的下端排出烘箱。

公开(公告)号：US07668038B2

公开(公告)日：2010-02-23

申请号：US11984761

申请日：2007-11-21

申请人： Kyoung-Ho Kim

发明人： Kyoung-Ho Kim

IPC分类号： G11C8/18

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4085

摘要： A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal, the write command signal and a write recovery time control signal having a plurality of bits to generate a plurality of gated bank pre-charge control signals. Therefore, the semiconductor memory device may decrease a number of flip-flops required to control a write recovery time.

摘要翻译： 半导体存储器件可以包括时钟缓冲器，命令解码器和写恢复时间控制电路。 时钟缓冲器可以基于外部时钟信号产生内部时钟信号。 命令解码器可以通过解码外部命令信号来产生写命令信号。 写恢复时间控制电路可以基于内部时钟信号，写命令信号和具有多个位的写恢复时间控制信号，在波流管模式中选通多个存储体预充电控制信号，以产生多个 选通银行预充电控制信号。 因此，半导体存储器件可以减少控制写恢复时间所需的触发器数量。

公开(公告)号：US07619935B2

公开(公告)日：2009-11-17

申请号：US11680886

申请日：2007-03-01

申请人： Kyoung Ho Kim ,  Seong Jin Jang

发明人： Kyoung Ho Kim ,  Seong Jin Jang

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/002

摘要： A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

摘要翻译： 提供了一种电路和方法，用于控制在存储器件的局部和全局输入/输出线之间起作用的晶体管的栅极电压，该电路包括本地输入/输出线，本地输入/输出多路复用器的本地信号 与本地输入/输出线的通信，与本地从/到全局输入/输出多路复用器进行信号通信的全局输入/输出线，以及具有输入节点和输出节点的本地输入/输出控制器， 所述输入节点被设置用于接收指示输入或输出操作的信号，并且所述输出节点与所述本地输入/输出多路复用器的门相信号通信，以在所述输入/输出多路复用器中提供第一或第二电平的门信号 在存在输入操作的情况下存在输出操作和第三级的门信号。

公开(公告)号：US20090268528A1

公开(公告)日：2009-10-29

申请号：US12385121

申请日：2009-03-31

申请人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

发明人： Dae-Hyun Kim ,  Kwang-il Park ,  Kyoung-Ho Kim ,  Hyun-Jin Kim ,  Hye-Ran Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/08 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4091

摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

摘要翻译： 示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。 读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

公开(公告)号：US07609584B2

公开(公告)日：2009-10-27

申请号：US11594807

申请日：2006-11-09

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20090128994A1

公开(公告)日：2009-05-21

申请号：US11921195

申请日：2006-09-06

申请人： Tae Whan Yeu ,  Kyoung Ho Kim ,  Jee Young Yoo ,  Ue Jin Lee

发明人： Tae Whan Yeu ,  Kyoung Ho Kim ,  Jee Young Yoo ,  Ue Jin Lee

IPC分类号： H01G9/155 ,  B05D5/12

CPC分类号： H01G11/38 ,  H01G9/058 ,  Y02E60/13 ,  Y10T29/417

摘要： A capacitor comprising an electrode made from an electroconductive material and activated carbon in combination with quaternary ammonium tosylate, and a method for manufacturing the same. The method enables the preparation of a high capacitance electrode without special facilities. The capacitor exhibits high specific capacitance and a high energy density.

摘要翻译： 一种电容器，其包含由导电材料制成的电极和与季铵甲苯磺酸盐结合的活性炭及其制造方法。 该方法能够制备没有特殊设备的高电容电极。 电容器具有高比电容和高能量密度。

公开(公告)号：US07357231B2

公开(公告)日：2008-04-15

申请号：US11272744

申请日：2005-11-15

申请人： Sung Kwang Kim ,  Yu Jeub Ha ,  Yun Ic Hwang ,  Seok Weon Hong ,  Pung Yeun Cho ,  Kyoung Ho Kim ,  Kil Young Lee ,  Cheol Jin Kim ,  Tae Ho Kim ,  Sang Hyun Kang

发明人： Sung Kwang Kim ,  Yu Jeub Ha ,  Yun Ic Hwang ,  Seok Weon Hong ,  Pung Yeun Cho ,  Kyoung Ho Kim ,  Kil Young Lee ,  Cheol Jin Kim ,  Tae Ho Kim ,  Sang Hyun Kang

IPC分类号： F16D57/00

CPC分类号： E05F3/14 ,  E05D7/081 ,  E05F3/20 ,  E05F5/02 ,  E05Y2201/21 ,  E05Y2201/254 ,  E05Y2201/266 ,  E05Y2201/416 ,  E05Y2900/308 ,  F24C15/023 ,  Y10T16/52

摘要： A door damper. The door damper includes a rotational shaft rotatably coupled to a door, a rotating resistance unit to generate rotating resistance to the rotational shaft, and a latching device latched to the rotational shaft and the door so as to allow the door and the rotational shaft to rotate together in a predetermined region. The latching device includes a free rotating section enabling free rotation of the door at an initial stage of opening the door, and a latching section enabling the latching device to be latched to the rotational shaft and the door at a final stage of opening the door so as to allow the door and the rotational shaft to rotate together. With the door damper, the door of electronic appliances can be smoothly opened without impact, and can be easily closed.

摘要翻译： 门阻尼器 门阻尼器包括可旋转地联接到门的旋转轴，用于产生对旋转轴的旋转阻力的旋转阻力单元和锁定到旋转轴和门的闩锁装置，以允许门和旋转轴旋转 一起在预定区域。 闩锁装置包括自由旋转部分，其能够在打开门的初始阶段使门能够自由旋转;以及闩锁部分，其能够在打开门的最后阶段将闩锁装置锁定到旋转轴和门 以允许门和旋转轴一起旋转。 使用门阻尼器，可以平稳地打开电子设备的门而不受冲击，并且可以容易地关闭。

公开(公告)号：US20070115751A1

公开(公告)日：2007-05-24

申请号：US11594807

申请日：2006-11-09

申请人： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号中的一个来输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20070069788A1

公开(公告)日：2007-03-29

申请号：US11519252

申请日：2006-09-12

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

IPC分类号： H03K3/00

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356156

摘要： An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

摘要翻译： 半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。 第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。 因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。