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    Semiconductor memory device post-repair circuit and method
    1.
    发明授权
    Semiconductor memory device post-repair circuit and method 有权
    半导体存储器件修复后电路及方法

    公开(公告)号：US06704228B2

    公开(公告)日：2004-03-09

    申请号：US10160703

    申请日：2002-05-30

    申请人： Seong-Jin Jang ,  Kyu-Hyoun Kim

    发明人： Seong-Jin Jang ,  Kyu-Hyoun Kim

    IPC分类号： G11C2900

    CPC分类号： G11C29/785

    摘要： The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (“post repair”) using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

    摘要翻译： 使用采用两种类型的冗余编程的冗余存储器线路控制电路来改进通过用冗余单元替换这些单元来修复存储器阵列中的有缺陷的单元的能力。 当存储器阵列通过例如切割激光熔丝处于晶片状态时，大多数或全部冗余存储器线可被编程。 但是，在使用例如切断电保险丝的命令之后，可以在器件封装（“后修复”）之后至少编写一条存储器线。 优选地，可以在可以使用激光熔丝编程的相同冗余存储器线中选择用于后修复的冗余存储器线。 这样，如果需要，所有冗余存储器线路都可用于激光修复，同时也可以在确定冗余存储器线路无缺陷之后，选择冗余存储器线进行后期修复。 这增加了设备可修复的可能性，并且不会通过预先将其专用于激光或后修复而不必要地浪费冗余的存储器线。

    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    3.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same
    4.
    发明授权
    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same 有权
    包括虚拟位线和字线的半导体存储单元阵列和具有其的半导体存储器件

    公开(公告)号：US08514610B2

    公开(公告)日：2013-08-20

    申请号：US13616039

    申请日：2012-09-14

    申请人： Sang-Woong Shin ,  Seong-Jin Jang

    发明人： Sang-Woong Shin ,  Seong-Jin Jang

    IPC分类号： G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/24

    摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.

    摘要翻译： 半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。 虚拟位线位于位线的外部区域。 虚拟字线在字线的外部区域。 虚拟位线保持在浮置状态。 虚拟字线保持关闭电压。

    SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE, A PARALLEL INTERFACE SYSTEM AND METHODS THEREOF 有权
    半导体器件，并行接口系统及其方法

    公开(公告)号：US20130135956A1

    公开(公告)日：2013-05-30

    申请号：US13483719

    申请日：2012-05-30

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    IPC分类号： G11C7/22

    CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

    摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

    摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same
    6.
    发明授权
    Semiconductor memory cell array including dummy bit-line and word-line and semiconductor memory device having the same 有权
    包括虚拟位线和字线的半导体存储单元阵列和具有其的半导体存储器件

    公开(公告)号：US08295114B2

    公开(公告)日：2012-10-23

    申请号：US12656984

    申请日：2010-02-22

    申请人： Sang-Woong Shin ,  Seong-Jin Jang

    发明人： Sang-Woong Shin ,  Seong-Jin Jang

    IPC分类号： G11C7/02

    CPC分类号： G11C7/02 ,  G11C7/14 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/24

    摘要： A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage.

    摘要翻译： 半导体存储单元阵列包括多个位线，多个字线，多个存储单元，多个虚拟存储单元，多个虚拟位线和多个虚拟字线。 虚拟位线位于位线的外部区域。 虚拟字线在字线的外部区域。 虚拟位线保持在浮置状态。 虚拟字线保持关闭电压。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    8.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL
    9.
    发明申请
    BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL 有权
    位线感测放大器，包含其的存储器核心和从存储器单元感测电荷的方法

    公开(公告)号：US20110205822A1

    公开(公告)日：2011-08-25

    申请号：US13006832

    申请日：2011-01-14

    申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： G11C7/06 ,  G01R19/00

    CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

    摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

    摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。