公开(公告)号：US20110241733A1

公开(公告)日：2011-10-06

申请号：US12981453

申请日：2010-12-29

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03K5/01

CPC分类号： G11C7/1066 ,  G11C7/222

摘要： An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.

摘要翻译： 输出使能信号生成电路包括等待解码器，锁存单元，延迟复用器和使能设置单元。 延迟解码器被配置为解码模式寄存器集代码并生成第一和第二CAS等待时间信息。 锁存单元被配置为输出锁存的第一和第二等待时间信息作为第一和第二等待时间信号。 延迟复用器被配置为响应于芯片选择信号而输出第一或第二等待时间信号作为输出CAS等待时间信号。 使能设置单元被配置为设置输出使能信号的使能定时。

公开(公告)号：US20110074479A1

公开(公告)日：2011-03-31

申请号：US12883730

申请日：2010-09-16

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

摘要翻译： 延迟锁定环（DLL）装置包括将参考时钟转换为上升时钟的第一延迟单元。 第二延迟单元将参考时钟转换为下降时钟，复制延迟单元复制延迟上升时钟。 第一相位检测器比较参考时钟和延迟上升时钟的相位，以输出对应于比较相位的第一检测信号。 控制器根据第一相位检测器的第一检测信号，将上升时钟的上升沿与参考时钟的上升沿同步。 第二相位检测器比较同步上升时钟和同步时钟的相位，以输出对应于比较相位的第二检测信号。 DLL装置通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏差。

公开(公告)号：US20100301911A1

公开(公告)日：2010-12-02

申请号：US12855244

申请日：2010-08-12

申请人： Hyun Woo LEE ,  Won Joo YUN

发明人： Hyun Woo LEE ,  Won Joo YUN

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0995 ,  H03L2207/06

摘要： A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

摘要翻译： 提出了具有时钟信号发生电路和数据输出电路的半导体存储装置。 该装置包括延迟锁定环（DLL），锁相环（PLL），频率鉴别单元和数据输出缓冲器。 DLL电路被配置为负时延时钟信号以产生DLL时钟信号。 PLL电路被配置为接收DLL时钟信号以响应于DLL时钟信号的频率产生控制电压，并且产生与控制电压电平对应的频率的PLL时钟信号。 频率鉴别单元被配置为根据控制电压的电平来识别DLL时钟信号的频率，以产生频率鉴别信号。 数据输出缓冲器配置为接收DLL时钟信号或PLL时钟信号以缓冲输出数据信号。

公开(公告)号：US20100156486A1

公开(公告)日：2010-06-24

申请号：US12428507

申请日：2009-04-23

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818

摘要： A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.

摘要翻译： 延迟锁定环路（DLL）电路包括延迟线，其被配置为通过响应于延迟控制信号延迟参考时钟信号来产生延迟时钟信号，延迟线具有两个或更多个初始激活点，其中初始激活点为 根据延迟控制信号的初始值选择; 延迟补偿单元，被配置为通过将所述延迟时钟信号延迟预定时间来产生反馈时钟信号; 相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号; 以及延迟控制单元，被配置为响应于相位检测信号而产生延迟控制信号。

公开(公告)号：US20070200604A1

公开(公告)日：2007-08-30

申请号：US11677619

申请日：2007-02-22

申请人： Won Joo YUN ,  Hyun Woo LEE

发明人： Won Joo YUN ,  Hyun Woo LEE

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： The present invention relates to a delay locked loop (DLL) apparatus. The DLL apparatus includes: a first delay means converting a reference clock into a rising clock; a second delay means converting the reference clock into a falling clock by delaying the reference clock; a replica delay unit replica-delaying the rising clock delayed by the first delay means; a first phase detection means comparing the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases; a control means synchronizing the rising edge of the rising clock with the rising edge of the reference clock in accordance with the first detection signal of the first phase detection means; and a second phase detection means comparing the phases of the rising clock synchronized by the control means and the synchronization clock to output a second detection signal corresponding to the compared phases. Accordingly, there is provided a DLL apparatus for compensating for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.

摘要翻译： 延迟锁定环（DLL）装置技术领域本发明涉及延迟锁定环（DLL）装置。 DLL装置包括：将参考时钟转换为上升时钟的第一延迟装置; 第二延迟装置通过延迟参考时钟将参考时钟转换成下降时钟; 复制延迟单元复制延迟由第一延迟装置延迟的上升时钟; 第一相位检测装置，比较参考时钟和延迟上升时钟的相位，以输出对应于所比较的相位的第一检测信号; 控制装置根据第一相位检测装置的第一检测信号使上升时钟的上升沿与基准时钟的上升沿同步; 以及第二相位检测装置，比较由控制装置同步的上升时钟的相位和同步时钟，以输出对应于比较相位的第二检测信号。 因此，提供了一种DLL装置，用于通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏斜。

公开(公告)号：US20120174135A1

公开(公告)日：2012-07-05

申请号：US13339471

申请日：2011-12-29

申请人： Min Shik ROH ,  Hyun Woo LEE ,  Min SONG

发明人： Min Shik ROH ,  Hyun Woo LEE ,  Min SONG

IPC分类号： G11B17/05

CPC分类号： G11B17/056 ,  G11B33/08

摘要： An optical device is provided including a tray body linearly moving and loading an optical disk. A case guide is configured to guide the linear movement of the tray body. A damper is interposed between the tray body and the case guide to attenuate vibration of the tray body.

摘要翻译： 提供了一种光学装置，其包括线状移动并装载光盘的托盘主体。 壳体引导件构造成引导托盘主体的线性移动。 在托盘主体和壳体引导件之间插入阻尼器，以减弱托盘主体的振动。

公开(公告)号：US20120163348A1

公开(公告)日：2012-06-28

申请号：US13333877

申请日：2011-12-21

申请人： Seung Hee HAN ,  Min Seok NOH ,  Yeong Hyeon KWON ,  Hyun Woo LEE ,  Dong Cheol KIM ,  Jin Sam KWAK

发明人： Seung Hee HAN ,  Min Seok NOH ,  Yeong Hyeon KWON ,  Hyun Woo LEE ,  Dong Cheol KIM ,  Jin Sam KWAK

IPC分类号： H04W72/04

CPC分类号： H04J11/0073 ,  H04J13/0062 ,  H04J2011/0096 ,  H04L5/0007 ,  H04L5/0048 ,  H04L5/0066 ,  H04L7/0087 ,  H04L25/0226 ,  H04L25/0228 ,  H04L27/2605 ,  H04L27/2613 ,  H04L27/2614 ,  H04L27/2615 ,  H04L27/2647 ,  H04L27/2657 ,  H04W56/0015

摘要： A sequence generation method for allowing a reception end to effectively detect a sequence used for a specific channel of an OFDM communication system, and a signal transmission/reception method using the same are disclosed. During the sequence generation, an index is selected from among the index set having the conjugate symmetry property between indexes, and a specific part corresponding to the frequency “0” is omitted from a transmitted signal. In addition, a reception end can calculate a cross-correlation value between a received (Rx) signal and each sequence using only one cross-correlation calculation based on the conjugate symmetry property.

摘要翻译： 公开了一种用于允许接收端有效地检测用于OFDM通信系统的特定信道的序列的序列生成方法和使用该序列的信号发送/接收方法。 在序列生成期间，从索引之间具有共轭对称性的索引集合中选择索引，并且从发送信号中省略与频率“0”相对应的特定部分。 此外，接收端可以基于共轭对称性仅使用一次互相关计算来计算接收的（Rx）信号和每个序列之间的互相关值。

公开(公告)号：US20120108279A1

公开(公告)日：2012-05-03

申请号：US13341390

申请日：2011-12-30

申请人： Min Seok NOH ,  Seung Hee HAN ,  Yeong Hyeon KWON ,  Hyun Woo LEE ,  Dong Cheol KIM ,  Jin Sam KWAK

发明人： Min Seok NOH ,  Seung Hee HAN ,  Yeong Hyeon KWON ,  Hyun Woo LEE ,  Dong Cheol KIM ,  Jin Sam KWAK

IPC分类号： H04B7/24

CPC分类号： H04J13/0062 ,  H04J11/005 ,  H04L5/0016 ,  H04L5/0048 ,  H04L5/0051 ,  H04L5/0053 ,  H04L23/02 ,  H04L27/2607 ,  H04L27/261 ,  H04L27/2613

摘要： A method for a base station to receive a reference signal sequence from one or more devices within a cell of the base station in a multiple cell environment includes providing the one or more devices with information about the reference signal sequence, wherein the reference signal sequence is defined by a cyclic shift of a sequence within a sequence group identified by a group index (u), wherein the group index (u) is defined according to the cell in the multiple cell environment, wherein the sequence is given by a cyclic extension of a Zadoff Chu (ZC) sequence having an index (q) and a length (NZCRS), and wherein the index (q) is given by using the group index (u) and the length (NZCRS), and receiving the reference signal sequence from one or more of the one or more devices.

摘要翻译： 一种用于基站在多小区环境中从所述基站的小区内的一个或多个设备接收参考信号序列的方法包括向所述一个或多个设备提供关于所述参考信号序列的信息，其中所述参考信号序列是 通过由组索引（u）标识的序列组内的序列的循环移位定义，其中所述组索引（u）根据所述多小区环境中的小区来定义，其中所述序列由 具有索引（q）和长度（NZCRS）的Zadoff Chu（ZC）序列，并且其中通过使用组索引（u）和长度（NZCRS）给出索引（q），并且接收参考信号序列 来自所述一个或多个设备中的一个或多个。

公开(公告)号：US20120044002A1

公开(公告)日：2012-02-23

申请号：US12983187

申请日：2010-12-31

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： H03L7/06 ,  H03K7/08

CPC分类号： H03L7/0816

摘要： A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.

摘要翻译： 一种半导体装置，包括：更新脉冲发生单元，被配置为基于时钟的频率在每第一周期产生更新脉冲;以及控制单元，被配置为响应于输入信号和更新脉冲来控制输出信号，使得 输出信号根据输入信号而变化。

公开(公告)号：US20110242905A1

公开(公告)日：2011-10-06

申请号：US12981815

申请日：2010-12-30

申请人： Ki Han KIM ,  Hyun Woo LEE

发明人： Ki Han KIM ,  Hyun Woo LEE

IPC分类号： G11C7/10

CPC分类号： H03K3/02 ,  G11C5/02

摘要： A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

摘要翻译： 模块控制电路包括：输入单元，被配置为从多个数据输入/输出引脚接收多个数据信号，并输出识别信号和内部命令信号。 闩锁单元被配置为根据第一使能信号锁定识别信号以输出第一组识别信号，根据第二使能信号锁存识别信号以输出第二组识别信号，并锁存内部命令信号 根据第二使能信号输出组指令信号。 比较器被配置为将第一组识别信号与第二组识别信号进行比较，并产生选择信号。 复用器被配置为响应于选择信号选择组命令信号和模块命令信号之一作为输入命令。