Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
Abstract:
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets.
Abstract:
An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize a digital data signal; align the equalized digital data signal; determine a detector reliability metric based at least in part on the aligned equalized digital data signal; perform an iterative decoding process to determine a decoded digital data signal using the detector reliability metric; adjust the aligned equalized digital data signal using the decoded digital data signal; and repeat at least determining the detector reliability metric and performing the iterative decoding process using the adjusted equalized digital data signal.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one particular example, a method is disclosed that includes: querying an input data set for an actual sync mark; forcing a proxy sync mark where the actual sync mark is not found in the input data set; applying data processing to the input data set to yield a processed output; correlating a potion of the processed output with a corresponding portion of the input data set to yield a true sync location; calculating a difference between the true sync location and the location of the forced sync mark to yield an offset; re-forcing the proxy sync mark based upon the offset; and re-applying the data processing to the input data set aligned using the re-forced proxy sync mark to yield a re-processed output.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. Some embodiments include one or both of a multi-algorithm data encoder circuit and/or a multi-algorithm data decoder circuit. In some cases, a first algorithm encoding is applied on a first section by section basis to a user data set yield an encoded portion; and a second algorithm encoding is applied on a second section by section basis to a data set derived from a subset of the encoded portion.
Abstract:
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including selective complexity data decoding.
Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
Abstract:
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for adapting noise predictive filters for inter-track interference cancellation in a data processing system.
Abstract:
Methods and systems for estimating MRA for a hard disk drive are described. The methods and systems described herein provide for real time estimating and correcting magneto-resistive head asymmetry (MRA) in a hard disk drive using analog-to-digital convertor (ADC) samples or counts. Generally, ADC outputs may be obtained by injecting MRA at known values, where an estimated MRA may be derived in real time by applying an equation using particular ADC output values. Once an estimated MRA is obtained, MRA correction may be performed when the estimated MRA is larger than a threshold value, such as by adjusting a channel MRA compensation coefficient.