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    SYNCHRONIZED RATE CONTROL AT RATE LIMITER
    31.
    发明公开
    SYNCHRONIZED RATE CONTROL AT RATE LIMITER 审中-公开

    公开(公告)号：US20230361900A1

    公开(公告)日：2023-11-09

    申请号：US18107442

    申请日：2023-02-08

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Liron Mula ,  Natan Manevich

    IPC: H04J3/06 ,  H04L47/25

    CPC classification number: H04J3/0652 ,  H04L47/25 ,  H04J3/0667

    Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.

    Clock synchronization using digitally controlled oscillator
    37.
    发明申请
    Clock synchronization using digitally controlled oscillator 有权

    公开(公告)号：US20250055667A1

    公开(公告)日：2025-02-13

    申请号：US18420822

    申请日：2024-01-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Nir Laufer ,  Wojciech Wasko ,  Maciej Machnikowski ,  Doron Fael ,  Arnon Sattinger

    IPC: H04L7/00 ,  H04L7/04

    Abstract: In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

    INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM
    38.
    发明申请
    INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM 有权

    公开(公告)号：US20250036503A1

    公开(公告)日：2025-01-30

    申请号：US18916370

    申请日：2024-10-15

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

    IPC: G06F11/07

    Abstract: A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.

    Intelligent exposure of hardware latency statistics within an electronic device or system
    39.
    发明授权
    Intelligent exposure of hardware latency statistics within an electronic device or system 有权

    公开(公告)号：US12158795B2

    公开(公告)日：2024-12-03

    申请号：US18074751

    申请日：2022-12-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

    IPC: G06F1/04 ,  G06F11/07

    Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

    PHYSICAL LAYER SYNCHRONIZATION
    40.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240373379A1

    公开(公告)日：2024-11-07

    申请号：US18225525

    申请日：2023-07-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

    IPC: H04W56/00

    Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

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