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    BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES
    31.
    发明申请
    BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES 有权

    公开(公告)号：US20250149094A1

    公开(公告)日：2025-05-08

    申请号：US19008495

    申请日：2025-01-02

    Applicant: Micron Technology, Inc.

    Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

    Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

    Adaptive enhanced corrective read based on write and read temperature
    33.
    发明授权
    Adaptive enhanced corrective read based on write and read temperature 有权

    公开(公告)号：US12242755B2

    公开(公告)日：2025-03-04

    申请号：US18434616

    申请日：2024-02-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu ,  Nagendra Prasad Ganesh Rao

    IPC: G06F3/06

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

    Bias voltage schemes during pre-programming and programming phases
    34.
    发明授权
    Bias voltage schemes during pre-programming and programming phases 有权

    公开(公告)号：US12217801B2

    公开(公告)日：2025-02-04

    申请号：US18076537

    申请日：2022-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

    Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

    ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR RESPECTIVE GROUPS OF WORDLINES IN A MEMORY SUB-SYSTEM
    37.
    发明公开
    ADAPTIVE TIME SENSE PARAMETERS AND OVERDRIVE VOLTAGE PARAMETERS FOR RESPECTIVE GROUPS OF WORDLINES IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240319881A1

    公开(公告)日：2024-09-26

    申请号：US18662940

    申请日：2024-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Zhenming Zhou ,  Ching-Huang Lu ,  Murong Lang

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

    MANAGING TRAP-UP IN A MEMORY SYSTEM
    38.
    发明公开
    MANAGING TRAP-UP IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240233842A1

    公开(公告)日：2024-07-11

    申请号：US18393354

    申请日：2023-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Chi Ming W. Chu ,  Avinash Rajagiri ,  Ching-Huang Lu ,  Kenneth W. Marr

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28

    CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

    Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.

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