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公开(公告)号：US12131783B2
公开(公告)日：2024-10-29
申请号：US17540752
申请日：2021-12-02
Applicant: Micron Technology, Inc.
Inventor： Xiangyu Yang , Ching-Huang Lu
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/3427
Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including initiating a read recovery process associated with a block of the memory array. The block includes wordlines at an initial voltage. The operations further include causing an early discharge sequence to be performed on a first set of wordlines of the wordlines during the read recovery process to alleviate latent read disturb. The early discharge sequence includes ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the wordlines at the initial voltage.
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公开(公告)号：US12124705B2
公开(公告)日：2024-10-22
申请号：US17848061
申请日：2022-06-23
Applicant: Micron Technology, Inc.
Inventor： Pitamber Shukla , Ching-Huang Lu , Devin Batutis
CPC classification number: G06F3/0619 , G06F3/0608 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/002 , G06F11/076
Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.
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3.发明公开公开(公告)号：US20240249776A1
公开(公告)日：2024-07-25
申请号：US18411532
申请日：2024-01-12
Applicant: Micron Technology, Inc.
Inventor： Vinh Quang Diep , Ching-Huang Lu , Yingda Dong
CPC classification number: G11C16/102 , G11C16/08 , G11C16/12
Abstract: A request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device is identified. At a first time during application of a programming voltage to the target wordline, causing a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device. At a second time during application of the programming voltage to the target wordline, causing a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, where the first adjusted pass through voltage is greater than the second pass through voltage.
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公开(公告)号：US20240071530A1
公开(公告)日：2024-02-29
申请号：US18233420
申请日：2023-08-14
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Hong-Yan Chen , Yingda Dong
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102
Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.
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公开(公告)号：US20240062827A1
公开(公告)日：2024-02-22
申请号：US18234289
申请日：2023-08-15
Applicant: Micron Technology, Inc.
Inventor： Ronit Roneel Prakash , Pitamber Shukla , Ching-Huang Lu , Murong Lang , Zhenming Zhou
CPC classification number: G11C16/16 , G11C16/3445 , G11C16/102 , G11C16/26
Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.
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Patent Agency Ranking
公开(公告)号：US20230418742A1
公开(公告)日：2023-12-28
申请号：US18203223
申请日：2023-05-30
Applicant: Micron Technology, Inc.
Inventor： Deping He , Ching-Huang Lu
CPC classification number: G06F12/0292 , G11C16/0483 , G11C16/10
Abstract: A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.
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7.发明公开公开(公告)号：US20240311042A1
公开(公告)日：2024-09-19
申请号：US18671855
申请日：2024-05-22
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Ching-Huang Lu , Murong Lang
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that a temperature associated with the memory device satisfies a threshold criterion; determining a memory access operation type of the memory access operation; and performing the memory access operation on the set of cells associated with the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the memory access operation type and the temperature associated with the memory device.
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公开(公告)号：US20240281148A1
公开(公告)日：2024-08-22
申请号：US18443584
申请日：2024-02-16
Applicant: Micron Technology, Inc.
Inventor： Jiun-Horng Lai , Pitamber Shukla , Ching-Huang Lu , Chengkuan Yin , Ronit Roneel Prakash , Yoshiaki Fukuzumi
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679
Abstract: Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.
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9.发明授权公开(公告)号：US12068036B2
公开(公告)日：2024-08-20
申请号：US17887765
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Jiun-horng Lai , Pitamber Shukla , Ching-Huang Lu , Chengkuan Yin , Yoshiaki Fukuzumi
Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.
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公开(公告)号：US20240241664A1
公开(公告)日：2024-07-18
申请号：US18434616
申请日：2024-02-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhenming Zhou , Murong Lang , Ching-Huang Lu , Nagendra Prasad Ganesh Rao
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.
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