公开(公告)号：US20240071970A1

公开(公告)日：2024-02-29

申请号：US18237225

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05147 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/80097 ,  H01L2224/8019 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A semiconductor device assembly is described that includes two semiconductor dies. The semiconductor dies each include a layer of dielectric material and a reservoir of conductive material located adjacent to openings in the layer of dielectric material. The opening at the layer of dielectric material of the first semiconductor die and the opening at the layer of dielectric material of the second semiconductor die are aligned to create an interconnect opening. The reservoirs of conductive material are heated to volumetrically expand the reservoirs of conductive material past one another such that they contact at respective non-horizontal surfaces to form an interconnect electrically coupling the semiconductor dies. In this way, a connected semiconductor device may be assembled.

公开(公告)号：US20230395516A1

公开(公告)日：2023-12-07

申请号：US18452695

申请日：2023-08-21

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5384 ,  G11C5/025 ,  G11C5/06 ,  H01L21/50 ,  H01L21/76877 ,  H01L23/5385 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US20230066395A1

公开(公告)日：2023-03-02

申请号：US17857967

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Bang-Ning Hsu ,  Kyle K. Kirby

IPC: H01L23/00

Abstract: A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.

公开(公告)号：US20220246569A1

公开(公告)日：2022-08-04

申请号：US17674487

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

公开(公告)号：US11239207B1

公开(公告)日：2022-02-01

申请号：US16938861

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

公开(公告)号：US11239169B1

公开(公告)日：2022-02-01

申请号：US16938844

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US20220028830A1

公开(公告)日：2022-01-27

申请号：US16938861

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

公开(公告)号：US20220028789A1

公开(公告)日：2022-01-27

申请号：US16938844

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US11088114B2

公开(公告)日：2021-08-10

申请号：US16671546

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/60

Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

公开(公告)号：US11056443B2

公开(公告)日：2021-07-06

申请号：US16554986

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L25/065 ,  H01L21/74 ,  H01L21/56 ,  H01L21/48 ,  H01L23/492

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.