公开(公告)号：US20240063184A1

公开(公告)日：2024-02-22

申请号：US17889914

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay ,  Bang-Ning Hsu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06551 ,  H01L2225/06586

Abstract: A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

公开(公告)号：US20240071969A1

公开(公告)日：2024-02-29

申请号：US18220734

申请日：2023-07-11

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street ,  Bang-Ning Hsu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48229 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: Semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. Each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. The first die is coupled to the third die via an interconnect portion of the second die. Further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (CMOS) circuitry accessing the active cells, and the first die can include backend of line (BEOL) circuitry associated with the active cells and CMOS circuitry.

公开(公告)号：US20240071987A1

公开(公告)日：2024-02-29

申请号：US17898356

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Bang-Ning Hsu ,  Kyle K. Kirby ,  Byung Hoon Moon

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80222 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor die is provided, comprising a semiconductor substrate, a dielectric layer over the semiconductor substrate, a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate, and a region including a plurality of embedded nanoparticles in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the plurality of embedded nanoparticles to an externally-applied field.

公开(公告)号：US20240071972A1

公开(公告)日：2024-02-29

申请号：US17823162

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Hidenori Yamaguchi ,  Keizo Kawakita ,  Bang-Ning Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/11464 ,  H01L2224/11912 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14134 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.

公开(公告)号：US20230066395A1

公开(公告)日：2023-03-02

申请号：US17857967

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Bang-Ning Hsu ,  Kyle K. Kirby

IPC: H01L23/00

Abstract: A method for bonding semiconductor dies, resulting semiconductor devices, and associated systems and methods are disclosed. In some embodiments, the method includes depositing a first material on the first semiconductor die. The first material has a first outer surface and a first chemical composition at the first outer surface. The method also includes depositing a second material on the second semiconductor die. The second material has a second outer surface and a second chemical composition at the second outer surface that is different from the first chemical composition. The method also includes stacking the dies. The second outer surface of the second semiconductor die is in contact with the first outer surface of the first semiconductor die in the stack. The method also includes reacting the first outer surface with the second outer surface. The reaction causes the first outer surface to bond to the second outer surface.