公开(公告)号：US20220036940A1

公开(公告)日：2022-02-03

申请号：US16942588

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4094

Abstract: Apparatuses and methods including memory cells, digit lines, and sense amplifiers are described. An example apparatus includes a pair of digit lines including first and second digit lines, a sense amplifier coupled to the pair of digit lines and configured to amplify a voltage difference between the first and second digit lines when activated, and a plurality of memory cells. A memory cell of the plurality of memory cells includes a first node coupled to the first digit line and includes a second node coupled to the second digit line. The memory cell of the plurality of memory cells is configured to store a respective voltage and/or charge at a respective cell node and couple the respective voltage and/or charge to the first node when activated.

公开(公告)号：US11205470B2

公开(公告)日：2021-12-21

申请号：US16853417

申请日：2020-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sang-Kyun Park ,  Tae H. Kim

IPC: G11C11/408 ,  G11C5/06 ,  G11C11/56 ,  G11C11/4074

Abstract: A main word driver may be coupled to a subword driver to drive a main word line to select the subword driver. The main word driver may include a first transistor having a body and source/drain both coupled to a well. The main word driver may include a well control circuit configured to bias the well. In some examples, the well control circuit may provide a first low potential to the well followed by a second low potential lower than the first potential responsive to a precharge command. The main word driver may include a second transistor coupled to the well control circuit to receive the first and second low potentials and couple the first and second low potentials to the main word line. The body of the second transistor may be coupled to the well. Additional transistors in the main word driver may also be coupled to the well.

公开(公告)号：US20210090625A1

公开(公告)日：2021-03-25

申请号：US17111311

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Tae H. Kim

IPC: G11C8/08 ,  G11C11/408

Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.

公开(公告)号：US10910049B2

公开(公告)日：2021-02-02

申请号：US16399197

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08

Abstract: A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-up circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state.

公开(公告)号：US10777236B2

公开(公告)日：2020-09-15

申请号：US16696246

申请日：2019-11-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim ,  Byung S. Moon

IPC: G11C5/14 ,  G11C8/10

Abstract: Methods and apparatuses are provided for driver circuits without voltage level shifters. An example apparatus includes a semiconductor device including a row decoder circuit that includes a driver circuit and a switching circuit. The driver circuit is configured to receive an input signal having a first logical value, a first voltage signal, and a configurable power signal. The driver circuit is further configured to provide an output signal having the first logical value based on the first signal having the first logical value. A voltage level of the input signal is based on the first voltage signal and a voltage level the output signal is based on the configurable voltage signal. The switching circuit is configured to receive the first voltage signal and a second voltage signal and to provide the configurable voltage signal having a voltage level of one of the first voltage signal or the second voltage signal.

公开(公告)号：US10734050B2

公开(公告)日：2020-08-04

申请号：US16405075

申请日：2019-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.

公开(公告)号：US10714167B2

公开(公告)日：2020-07-14

申请号：US16431500

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/22 ,  G11C5/02 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H01L27/108

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US10658024B2

公开(公告)日：2020-05-19

申请号：US16523653

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US10541008B2

公开(公告)日：2020-01-21

申请号：US16017826

申请日：2018-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher Kawamura ,  Tae H. Kim

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C8/10 ,  G11C7/12 ,  G11C11/4074

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.

公开(公告)号：US10431291B1

公开(公告)日：2019-10-01

申请号：US16058600

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.