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公开(公告)号：US07602231B2
公开(公告)日：2009-10-13
申请号：US11526060
申请日：2006-09-25
CPC分类号： H02M3/07
摘要： A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
摘要翻译： 电路包括多个级，每个级包括MOS晶体管和电容器，其一端连接到MOS晶体管的漏极和源极之一。 多个级通过MOS晶体管的级联连接而相互连接。 MOS晶体管的栅极在每个级中电连接到漏极和源极之一，并且用于至少一对相邻MOS晶体管的衬底电连接到该对之一的漏极和源极之一 。 背偏置效果被抑制，布局面积减小。 此外，在后续阶段提供串联连接的多个升压电容器，从而抑制每个电容器的击穿电压的劣化。
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公开(公告)号：US20090189226A1
公开(公告)日：2009-07-30
申请号：US12247647
申请日：2008-10-08
IPC分类号： H01L29/00
摘要： An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor.
摘要翻译： 除了独立的电源开关电路之外，电熔丝电路还包括多个熔丝位单元，每个熔丝位单元包括一个熔丝元件，其一端连接到电源开关电路的输出端，第一MOS晶体管连接 连接到熔丝元件的另一端，其中二极管作为ESD对策连接在地电位和电源开关电路之间。 熔丝位单元的晶体管的栅极氧化膜厚度等于低压逻辑型晶体管的栅极氧化膜厚度，而不是高电压I / O型晶体管的晶体管的栅极氧化膜厚度。
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公开(公告)号：US08094498B2
公开(公告)日：2012-01-10
申请号：US12792295
申请日：2010-06-02
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
摘要翻译： 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。
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公开(公告)号：US07623380B2
公开(公告)日：2009-11-24
申请号：US11526057
申请日：2006-09-25
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/105 , H01L27/11521 , H01L27/11558
摘要： A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
摘要翻译： 用于通过在浮动栅极中累积电荷来存储数据的非易失性半导体存储器件包括共享浮置栅极的多个MOS晶体管。 在器件中，在写入期间使用PMOS耦合并且在擦除期间使用n型耗尽MOS（DMOS）耦合。 与传统的三晶体管非易失性存储元件相比，通过PMOS将沟道反转电容耦合用于n型DMOS的耗尽电容的写入和耦合用于擦除，从而增加擦除速度而不增加面积。
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公开(公告)号：US07622982B2
公开(公告)日：2009-11-24
申请号：US11882974
申请日：2007-08-08
IPC分类号： H01H37/76
摘要： The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.
摘要翻译： 本发明提供一种电熔丝装置，包括：多个熔丝芯，每个熔丝芯具有电熔丝元件和串联连接到电熔丝元件的开关元件; 程序控制电路，通过与有效的程序时钟信号同步地依次移位程序控制传输信号并随后根据程序数据产生要发送到多个保险丝核心中的每一个开关元件的程序信号来产生程序移位信号 和程序移位信号; 以及程序时钟控制电路，其根据程序时钟使能信号控制编程时钟信号的导通状态和非导通状态，并且当所述程序时钟信号处于导通状态时，将所述程序时钟信号发送到所述程序控制电路 作为有效的程序时钟信号。
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公开(公告)号：US06333876B1
公开(公告)日：2001-12-25
申请号：US09536697
申请日：2000-03-28
IPC分类号： G11C700
CPC分类号： G11C29/802 , G11C29/848
摘要： The semiconductor memory device of the present invention has: a memory cell array including a plurality of memory cell groups and a redundant cell group having a plurality of redundant cells arranged in parallel with the memory cell groups; a cell selection circuit for allowing one of a plurality of cell selection lines to select a specific memory cell group; a defective cell designation section for outputting defective cell designation signals designating a predetected defective cell out of the plurality of memory cells; and a connection change circuit for electrically disconnecting the cell selection line selecting the memory cell group including the defective cell from the cell selection circuit and outputting an output signal from the cell selection circuit to the redundant cell group. The defective cell designation section includes: a plurality of defective cell designation circuits for outputting designation signals capable of designating the plurality of cell selection lines; and a defective cell designation signal generation circuit for generating and outputting the defective cell designation signals based on the designation signals output from the plurality of defective cell designation circuits. The number of the plurality of defective cell designation circuits is smaller than the number of the plurality of cell selection lines.
摘要翻译： 本发明的半导体存储器件具有：包括多个存储单元组的存储单元阵列和具有与存储单元组并联布置的多个冗余单元的冗余单元组;单元选择电路，用于允许 多个单元选择线，用于选择特定的存储单元组;缺陷单元指定单元，用于输出指定多个存储单元中预先检测的缺陷单元的缺陷单元指定信号;以及连接变换电路，用于电连接单元选择， 存储单元组，其包括来自单元选择电路的缺陷单元，并将来自单元选择电路的输出信号输出到冗余单元组。 有缺陷单元指定部分包括：多个缺陷单元指定电路，用于输出能够指定多个单元选择线的指定信号; 以及有缺陷单元指定信号产生电路，用于基于从多个有缺陷单元指定电路输出的指定信号产生和输出有缺陷单元指定信号。 多个有缺陷单元指定电路的数量小于多个单元选择线的数量。
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公开(公告)号：US6118723A
公开(公告)日：2000-09-12
申请号：US326230
申请日：1999-06-04
申请人： Masashi Agata , Toshiaki Kawasaki
发明人： Masashi Agata , Toshiaki Kawasaki
IPC分类号： G11C11/407 , G11C8/14 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/14
摘要： A semiconductor memory device includes: an array of memory cells that is divided into a plurality of sub-arrays; main word lines; sub-word lines; sub-word select lines; and sub-word drivers. A predetermined number of main word lines are associated with a block of sub-arrays arranged on the same row, and extend over all of these sub-arrays. A set of sub-word lines are provided per sub-array and driven by the same number of sub-word drivers corresponding thereto. Each sub-word select line consists of: a parallel portion, which is placed in parallel to the main word lines; and a plurality of vertical portions crossing the main word lines at right angles. Each sub-word driver is selected by specifying, in combination, one of the main word lines and one of the sub-word select lines. In this arrangement, a difference in signal propagation delay between a main word line and an associated parallel portion of a sub-word select line can be minimized, thus remarkably increasing the operating speed of a semiconductor memory device like a DRAM.
摘要翻译： 半导体存储器件包括：被分成多个子阵列的存储器单元的阵列; 主字线 子字线 子字选择行; 和子字驱动程序。 预定数量的主字线与布置在同一行上的子阵列块相关联，并且在所有这些子阵列上延伸。 每个子阵列提供一组子字线，并由相应数量的子字驱动器驱动。 每个子字选择线由以下部分组成：与主字线平行放置的平行部分; 以及与主字线交叉成直角的多个垂直部分。 通过组合指定主字线之一和子字选择线中的一个来选择每个子字驱动器。 在这种布置中，可以将主字线和子字选择线的相关联的并行部分之间的信号传播延迟的差最小化，从而显着增加诸如DRAM的半导体存储器件的操作速度。
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公开(公告)号：US20080036527A1
公开(公告)日：2008-02-14
申请号：US11882974
申请日：2007-08-08
IPC分类号： H01H37/76
摘要： The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.
摘要翻译： 本发明提供一种电熔丝装置，包括：多个熔丝芯，每个熔丝芯具有电熔丝元件和串联连接到电熔丝元件的开关元件; 程序控制电路，通过与有效的程序时钟信号同步地依次移位程序控制传输信号并随后根据程序数据产生要发送到多个保险丝核心中的每一个开关元件的程序信号来产生程序移位信号 和程序移位信号; 以及程序时钟控制电路，其根据程序时钟使能信号控制编程时钟信号的导通状态和非导通状态，并且当所述程序时钟信号处于导通状态时，将所述程序时钟信号发送到所述程序控制电路 作为有效的程序时钟信号。
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公开(公告)号：US5758009A
公开(公告)日：1998-05-26
申请号：US668738
申请日：1996-06-24
IPC分类号： H04N5/92 , G11B15/02 , G11B15/087 , H04N5/76 , H04N5/782 , H04N7/083 , H04N7/087 , H04N7/088
CPC分类号： H04N5/782
摘要： A video recording control device compares current and previous values indicated by an elapsed broadcast time information (TIS) of a program in an EDS (Extended Data Service) signal superimposed on a received television signal during its vertical blanking period, and controls the recording operation of a video recording apparatus employing the television signal according to the result of comparison. Therefore, the ending time of the program being recorded can be detected by utilizing the TIS of the EDS signal, and thus, even when the broadcast time of the program is extended without notifying in advance, the recording can be continued accordingly.
摘要翻译： 视频记录控制装置将叠加在其垂直消隐期间的接收电视信号上的EDS（扩展数据业务）信号中的程序的经过广播时间信息（TIS）表示的当前值和先前值进行比较，并控制记录操作 根据比较结果采用电视信号的视频记录装置。 因此，可以通过利用EDS信号的TIS来检测正在记录的节目的结束时间，因此即使在程序的广播时间延长而不事先通知的情况下，可以相应地继续记录。
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公开(公告)号：USD319335S
公开(公告)日：1991-08-27
申请号：US349295
申请日：1989-05-09
申请人： Toshiaki Kawasaki , Yoshiaki Hase
设计人： Toshiaki Kawasaki , Yoshiaki Hase
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