公开(公告)号：US20230163869A1

公开(公告)日：2023-05-25

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US20230132571A1

公开(公告)日：2023-05-04

申请号：US17520093

申请日：2021-11-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Dimitris Syrivelis ,  Liron Mula ,  Aviad Levy ,  Elad Mentovich

IPC: G06F21/72 ,  H04L9/08

Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.

公开(公告)号：US20230127568A1

公开(公告)日：2023-04-27

申请号：US17508998

申请日：2021-10-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: H04L29/06 ,  H04L29/08

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with. the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

公开(公告)号：US20230120745A1

公开(公告)日：2023-04-20

申请号：US17503383

申请日：2021-10-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Gil Levy ,  Liron Mula ,  Barak Gafni ,  Aviv Kfir

IPC: H04L12/861 ,  H04L12/879 ,  H04L12/933 ,  H04L12/925 ,  H04L12/911

Abstract: A network device includes multiple ports, packet processing circuitry, a memory and a reserved-memory management circuit (RMMC). The ports are to communicate packets over a network. The packet processing circuitry is to process the packets using a plurality of queues. The memory is to store a shared buffer. The RMMC is to allocate segments of the shared buffer to the queues, including allocating reserve segments of the shared buffer to selected queues that meet a reserve-allocation criterion.

公开(公告)号：US20220385590A1

公开(公告)日：2022-12-01

申请号：US17336080

申请日：2021-06-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Zachy Haramaty ,  Liron Mula ,  Alon Singer ,  Eduard Kvetny ,  Aviv Kfir

IPC: H04L12/801 ,  H04L12/861 ,  H04L12/707 ,  H04L29/06

Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US20140379836A1

公开(公告)日：2014-12-25

申请号：US13925868

申请日：2013-06-25

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Omer Zilberboim ,  Ofer Hayut ,  Yaron Haviv ,  Liron Mula ,  Noam Bloch ,  Nir Getter ,  Ariel Shachar

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F2211/1028 ,  H04L67/1097

Abstract: A network interface includes a host interface for communicating with a node, and circuitry which is configured to communicate with one or more other nodes over a communication network so as to carry out, jointly with one or more other nodes, a redundant storage operation that includes a redundancy calculation, including performing the redundancy calculation on behalf of the node.

Abstract translation: 网络接口包括用于与节点进行通信的主机接口，以及被配置为通过通信网络与一个或多个其他节点进行通信以便与一个或多个其他节点一起执行冗余存储操作的电路，所述冗余存储操作包括 冗余计算，包括代表节点执行冗余计算。

公开(公告)号：US20250165410A1

公开(公告)日：2025-05-22

申请号：US18516833

申请日：2023-11-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Liron Mula ,  Eyal Srebro

IPC: G06F13/16

Abstract: A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of portions, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit correlates egress ports with available portions among the plurality of portions as close as possible to a respective egress port.

公开(公告)号：US20250119382A1

公开(公告)日：2025-04-10

申请号：US18377473

申请日：2023-10-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Eran Gil Beracha

IPC: H04L47/125 ,  H04L47/36 ,  H04L47/62

Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes circuits to receive a packet, determine a size of the packet, determine a group of a plurality of groups of the packet based on the size of the packet, determine a port for the packet using a round-robin for the group of the packet, and send the packet via the port. Described systems include circuits to receive packet sizes from an application, initialize packet arbiter circuits based on the sizes, receive a packet associated with the application, determine a size of the packet, associate the packet with one of the packet arbiter circuits, and route the packet to a selected port.

公开(公告)号：US20250080460A1

公开(公告)日：2025-03-06

申请号：US18240549

申请日：2023-08-31

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mark Hummel ,  Jonathan Mercer Owen ,  Gregory Thorson ,  Glenn Dearth ,  Lion Levi ,  Lior Hodaya Bezen ,  Itamar Rabenstein ,  Ami Gidon Marelli ,  Roee Levy Leshem ,  Liron Mula ,  Alex Netes ,  Eyal Srebro

IPC: H04L45/7453 ,  H04L69/22

Abstract: Systems and methods herein are for one or more processing units to be associated with at least one switch or router and to enable the at least one switch or router to receive a communication from a source host machine, where the communication includes a request associated with memory access protocols of a memory space of a destination host machine, and where the communication is to be provided to the destination host machine to enable subsequent communications from the source host machine that are based in part on the memory access protocols received in response to the request.