公开(公告)号：US06469571B2

公开(公告)日：2002-10-22

申请号：US09996280

申请日：2001-11-28

申请人： Robert Esterl ,  Georg Braun

发明人： Robert Esterl ,  Georg Braun

IPC分类号： G05F302

CPC分类号： H02M3/073

摘要： A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to the inputs. Second electrodes of the pumping capacitors are in each case connected via a first circuit module to a supply potential (ground) and via a second circuit module to the output. Also present is a controllable short-circuiting element, the controllable path of which is disposed between the second electrodes of the two pumping capacitors.

摘要翻译： 电荷泵具有两个输入，每个输入用于输入时钟信号，以及用于输出泵浦输出电位的输出。 两个泵浦电容器连接到输入端。 泵送电容器的第二电极在每种情况下都经由第一电路模块连接到电源（地），并且经由第二电路模块连接到输出端。 还存在可控短路元件，其可控路径设置在两个泵浦电容器的第二电极之间。

公开(公告)号：US06327173B2

公开(公告)日：2001-12-04

申请号：US09740637

申请日：2000-12-18

申请人： Georg Braun

发明人： Georg Braun

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A method is described for reading and writing a ferroelectric memory. In ferroelectric memories, changes in a hysteresis curve on account of aging of the ferroelectric material are reduced or prevented by virtue of the fact that during reading and writing a complementary state is also written in and a capacitor voltage is reduced to 0 V before a memory cell is deactivated.

公开(公告)号：US6091625A

公开(公告)日：2000-07-18

申请号：US408479

申请日：1999-09-28

申请人： Georg Braun ,  Carlos Mazure-Espejo ,  Heinz Honigschmid ,  Andrej Majdic

发明人： Georg Braun ,  Carlos Mazure-Espejo ,  Heinz Honigschmid ,  Andrej Majdic

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.

摘要翻译： 集成存储器包括具有位线，字线和可写存储单元的单元阵列。 第一差分读出放大器具有连接到数据线对的连接，第一读出放大器在读访问操作期间从存储器单元之一读取信息，以便随后对其进行放大，并且第一读出放大器将信息写入一个 的存储单元。 相关信息通过数据线对传送为差分信号，并且在每次写入操作期间由第一读出放大器临时存储。 存储器还具有开关单元，通过该开关单元，数据线对连接到第一读出放大器的连接，用于相对于第一读出放大器的连接交换数据线对的线，这取决于开关状态 开关单元。 切换单元的切换状态在写访问操作期间至少改变一次，使得要被写入的信息由第一读出放大器最初以非反相的形式被写入相关存储器单元，然后以倒置形式写入相关的存储单元。 还提供了一种用于防止集成存储器中的存储单元中的老化的方法。

公开(公告)号：US07532523B2

公开(公告)日：2009-05-12

申请号：US11461380

申请日：2006-07-31

申请人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

发明人： Georg Braun ,  Christian Weis ,  Eckehard Plaettner

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G06F13/4086 ,  G11C5/04

摘要： Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

摘要翻译： 用于设置存储芯片的各种终端的方法和装置。 存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口以及连接到终端的控制电路 电路，以便根据接收到的控制命令信号设置电阻值。

公开(公告)号：US07149864B2

公开(公告)日：2006-12-12

申请号：US10777992

申请日：2004-02-12

申请人： Georg Braun ,  Andreas Jakobs

发明人： Georg Braun ,  Andreas Jakobs

IPC分类号： G06F12/02

CPC分类号： G06F12/0669

摘要： Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.

摘要翻译： 提供了用于在初始化模式期间将存储器布置地址分配给缓冲器芯片用于寻址连接到缓冲器芯片的一个或多个存储器配置的方法和装置。 缓冲器电路可以接收指定第一组可用存储器布置地址的第一初始化数据，并将第一组可用存储器配置地址中的一个或多个与连接到缓冲器芯片的一个或多个存储器配置相关联。 缓冲电路还可以产生指定在关联之后可用的可用存储器布置地址的集合的第二初始化数据。 第二初始化数据可以被发送到用于地址分配的另一缓冲电路或者返回到存储器访问控制单元。

公开(公告)号：US20060262613A1

公开(公告)日：2006-11-23

申请号：US11410320

申请日：2006-04-24

申请人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

发明人： Georg Braun ,  Eckehard Plaettner ,  Christian Weis ,  Andreas Jakobs

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.

摘要翻译： 提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入 数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。 该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

公开(公告)号：US07139290B2

公开(公告)日：2006-11-21

申请号：US10171098

申请日：2002-06-13

申请人： Georg Braun

发明人： Georg Braun

IPC分类号： H04J3/08 ,  G11C8/00

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

摘要： A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The storage data stream is then buffered into a register unit, where it is divided into data stream components buffered in corresponding data register components on the basis of a clock signal and an address signal provided to the register unit. Meanwhile, the mask data stream is buffered in a mask register of the register unit. A composite data stream is then formed by combining selected data stream components in response to information provided by a data mask unit from the mask data stream buffered in the mask register. Data corresponding to this composite data stream is then provided to the memory cell array for storage therein.

公开(公告)号：US07127553B2

公开(公告)日：2006-10-24

申请号：US10717337

申请日：2003-11-19

申请人： Alexander Benedix ,  Georg Braun ,  Bernd Klehn

发明人： Alexander Benedix ,  Georg Braun ,  Bernd Klehn

IPC分类号： H01L27/108

CPC分类号： G06F11/3409

摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

摘要翻译： 用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。 当有不同的应用程序时，使用与系统资源不同的访问策略。 还提供了一种用于确定对系统资源的最佳访问策略的方法。

公开(公告)号：US06894330B2

公开(公告)日：2005-05-17

申请号：US09783187

申请日：2001-02-14

申请人： Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

发明人： Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： G11C11/22

摘要： The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

摘要翻译： 读取或存储存储单元中的铁电晶体管的状态，并且在读取或存储期间在存储矩阵中的另外的存储单元中的另外的铁电晶体管的阈值电压增加或永久地增加。 还提供了包括铁电存储单元的存储器配置。

公开(公告)号：US06697279B2

公开(公告)日：2004-02-24

申请号：US09758300

申请日：2001-01-10

申请人： Ronny Schneider ,  Georg Braun

发明人： Ronny Schneider ,  Georg Braun

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell is present. As a result, without unacceptably increasing the access time, the interference pulses at the ferroelectric capacitors of the memory cells which are not being addressed at that particular time and which are generated by the reading out or writing of the addressed memory cell are reduced in such a way that they have virtually no further influence on the non-addressed memory cells.

摘要翻译： 存储器件具有串联连接的铁电存储器单元，其中存在由相应存储单元的铁电电容器的电阻器和/或晶体管组成的串联电路。 结果是，在没有不可接受地增加访问时间的情况下，在特定时间没有被寻址并且通过寻址的存储器单元的读出或写入而产生的存储单元的铁电电容器处的干扰脉冲被减少 它们对于非寻址存储器单元几乎没有进一步的影响。