公开(公告)号：US20100180081A1

公开(公告)日：2010-07-15

申请号：US12354219

申请日：2009-01-15

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Miles Robert Dooley ,  Michael Stephen Floyd ,  David Scott Ray ,  Bruce Joseph Ronchetti

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Miles Robert Dooley ,  Michael Stephen Floyd ,  David Scott Ray ,  Bruce Joseph Ronchetti

IPC分类号： G06F12/08 ,  G06F1/32 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F1/3203 ,  G06F12/0897 ,  G06F2212/6022

摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.

摘要翻译： 数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。 数据处理系统可以在第一模式和第二模式中操作。 预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

公开(公告)号：US20100037233A1

公开(公告)日：2010-02-11

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US07657772B2

公开(公告)日：2010-02-02

申请号：US10366437

申请日：2003-02-13

申请人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

发明人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

IPC分类号： G06F1/04 ,  G06F1/14

CPC分类号： H01L27/0248 ,  G01K7/425

摘要： An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

摘要翻译： 一种具有温度敏感电路（TSC）的集成电路，用于产生指示TSC附近的衬底温度的信号。 集成电路具有被配置为从至少一个TSC接收TSC信号并且将TSC信号转换成指示集成电路的温度的信号的电路。 热控制电路将集成电路温度与阈值进行比较，并在温度超过阈值时产生校正动作信号。 校正动作信号被提供给校正动作电路，优选地被配置为修改IC的操作以降低接近相应TSC的IC温度。

公开(公告)号：US20090249349A1

公开(公告)日：2009-10-01

申请号：US12059576

申请日：2008-03-31

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Richard James Eickemeyer ,  Susan Elizabeth Eisen ,  Michael Stephen Floyd ,  Hans Mikael Jacobson ,  Jeffrey R. Summers

IPC分类号： G06F9/46

CPC分类号： G06F9/4893 ,  Y02D10/24

摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

公开(公告)号：US20090199027A1

公开(公告)日：2009-08-06

申请号：US12023550

申请日：2008-01-31

申请人： Michael Stephen Floyd ,  Norman Karl James ,  Jeffrey William Kellington ,  Larry S. Leitner

发明人： Michael Stephen Floyd ,  Norman Karl James ,  Jeffrey William Kellington ,  Larry S. Leitner

IPC分类号： G06F1/26

CPC分类号： G06F9/4403 ,  G06F1/24 ,  G06F1/3203

摘要： Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).

摘要翻译： 示例性实施例提供计算机实现的方法和用于循环确定性开始的启动周期的系统。 初始化机制向微处理器施加电力。 初始化机制初始化微处理器的配置。 初始化机制初始化一个定时器。 初始化机制然后向微处理器发送时钟启动命令。 微处理器上的时钟启动。 在时钟启动时，定时器开始并允许临时瞬变，例如由于时钟切换开始时对电流的需求的大的瞬间变化而导致的电压下降。 响应于定时器达到目标值，中断单元发送系统复位中断。 响应于中断单元发送系统复位中断，指令提取单元获取第一条指令。 该操作对于微处理器存储元件（锁存器，阵列等）的其余部分的状态将是确定的。

公开(公告)号：US20090199020A1

公开(公告)日：2009-08-06

申请号：US12023536

申请日：2008-01-31

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。

公开(公告)号：US07453816B2

公开(公告)日：2008-11-18

申请号：US11054288

申请日：2005-02-09

申请人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

发明人： James Stephen Fields, Jr. ,  Michael Stephen Floyd ,  Benjiman Lee Goodman ,  Paul Frank Lecocq ,  Praveen S. Reddy

IPC分类号： G01R31/08 ,  G06F13/00

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed.If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20080134180A1

公开(公告)日：2008-06-05

申请号：US11960878

申请日：2007-12-20

申请人： Michael Stephen Floyd

发明人： Michael Stephen Floyd

IPC分类号： G06F9/46

CPC分类号： G06F9/3009 ,  G06F9/3851 ,  G06F9/5027 ,  G06F2209/5018

摘要： A processor supporting thread-execution-state-sensitive supervisory commands provides a mechanism for executing supervisory commands for live threads. The commands may be sent from a service processor or another primary processor in the system or may be supplied by the processor itself through supervisory software control. Since the state of execution of one or more threads may change dynamically within a processor core, an external processor will not know the thread execution state at the time the command operates. The method and apparatus provide a command set and logic that supports selective execution of particular commands directed at “alive” threads (or threads in some other determinable execution state), whereby the command is performed only on resources and/or execution units depending on the actual state of thread execution when the command operates within the processor.

摘要翻译： 支持线程执行状态敏感的监控命令的处理器提供了一种用于执行活动线程的监控命令的机制。 命令可以从系统中的服务处理器或另一主处理器发送，或者可以由处理器本身通过监控软件控制来提供。 由于一个或多个线程的执行状态可能在处理器核心内动态地改变，所以外部处理器将不知道命令操作时的线程执行状态。 该方法和装置提供一种命令集和逻辑，该命令集和逻辑支持选择性执行指向“活着”线程的特定命令（或某些其他可确定的执行状态的线程），由此该命令仅在资源和/或执行单元上执行，这取决于 当命令在处理器内运行时线程执行的实际状态。

公开(公告)号：US07305639B2

公开(公告)日：2007-12-04

申请号：US11055863

申请日：2005-02-11

申请人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

发明人： Michael Stephen Floyd ,  Joshua David Friedrich ,  Elspeth Anne Huston ,  Wolfgang Roesner ,  Rick John Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一验证机制以验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。

公开(公告)号：US07213169B2

公开(公告)日：2007-05-01

申请号：US10406650

申请日：2003-04-03

申请人： John Steven Dodson ,  Michael Stephen Floyd ,  Jerry Don Lewis ,  Gary Alan Morrison

发明人： John Steven Dodson ,  Michael Stephen Floyd ,  Jerry Don Lewis ,  Gary Alan Morrison

IPC分类号： G06F11/00

CPC分类号： G06F11/364

摘要： An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written. The time stamp trace record includes a count of the number of address transactions that were not converted to trace records.

摘要翻译： 公开了一种用于在分布式存储器对称多处理器系统中执行不精确总线跟踪的装置。 该装置包括总线跟踪宏（BTM）模块，其可以控制数据处理系统中的一个或多个存储器控制器所看到的窥探流量，并利用连接到存储器控制器的本地存储器来存储跟踪记录。 在BTM模块启用跟踪操作之后，BTM模块会窥探互连上的事务，并将包含在这些事务中的信息打包成与存储器控制器中写入缓冲区匹配的大小的数据块。 此外，BTM模块还包括一个丢弃的记录计数器，用于计数未转换为跟踪记录的地址事务数，因为所有的写入缓冲区已经完全满载。 写入缓冲区满满后，插入新的跟踪记录之前插入时间戳跟踪记录。 时间戳跟踪记录包括未转换为跟踪记录的地址事务数的计数。