公开(公告)号：US20120216210A1

公开(公告)日：2012-08-23

申请号：US13459398

申请日：2012-04-30

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/50

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派的事件来确定相对资源的使用，其可以包括仍然占据处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US08209698B2

公开(公告)日：2012-06-26

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US20100037233A1

公开(公告)日：2010-02-11

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US09003417B2

公开(公告)日：2015-04-07

申请号：US13459398

申请日：2012-04-30

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US07657893B2

公开(公告)日：2010-02-02

申请号：US10422025

申请日：2003-04-23

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： An accounting method and multi-threaded processor include a mechanism for accounting for processor resource usage by threads within programs. Relative resource use is determined by detecting a particular cycle state of threads active within the processor. If instructions are dispatched for all threads or no threads, the processor cycle is accounted equally to all threads. Alternatively if no threads are in the particular cycle state, the accounting may be made using a prior state, or in conformity with ratios of the threads' priority levels. If only one thread is in the particular cycle state, that thread is accounted the entire processor cycle. If multiple threads are dispatching, but less than all threads are dispatching, the processor cycle is billed evenly across the dispatching threads.

摘要翻译： 会计方法和多线程处理器包括用于计算程序内的线程的处理器资源使用的机制。 通过检测处理器内活动的线程的特定周期状态来确定相对资源的使用。 如果为所有线程或没有线程调度指令，则处理器周期与所有线程相等。 或者，如果没有线程处于特定周期状态，则可以使用先前状态进行计费，或者根据线程的优先级的比率来进行计费。 如果只有一个线程处于特定的循环状态，则该线程将占整个处理器周期。 如果多个线程正在调度，但是少于所有线程都调度，处理器周期将在调度线程中平均计费。

公开(公告)号：US07155600B2

公开(公告)日：2006-12-26

申请号：US10422648

申请日：2003-04-24

申请人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/485

摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.

摘要翻译： 用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。 然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配 如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。 然后，处理器开始执行剩余的已启用线程。

公开(公告)号：US07051221B2

公开(公告)日：2006-05-23

申请号：US10425399

申请日：2003-04-28

申请人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F1/32

CPC分类号： G06F9/3017 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D50/20

摘要： A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

摘要翻译： 微处理器包括具有动态功率节省电路的功能块，功能块控制电路和热控制单元。 功能块控制电路能够在检测到过温度条件时自动改变其相关功能块的性能特性。 热控制单元接收指示处理器温度超过阈值的过温度信号，并响应于该信号调用一个或多个功能块控制单元。 功能块控制单元通过减少处理器活动，降低处理器性能或两者来响应来自热控制单元的信号。 导致动态省电电路参与的活动减少。 功能块控制单元可以通过多种方式来抑制性能，包括减少处理器内可利用的并行性，暂停无序执行，减少有效的资源大小等。

公开(公告)号：US07305586B2

公开(公告)日：2007-12-04

申请号：US10424485

申请日：2003-04-25

申请人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

发明人： Richard William Doing ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  John Wesley Ward, III

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.

摘要翻译： 微处理器包括外部可访问端口和连接到端口的串行通信总线。 处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。 该卫星使外部代理可以通过串行总线直接向管线提供指令。 专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。 在执行指令期间，执行流水线可以访问专用寄存器。 以这种方式，卫星电路使外部代理能够访问架构状态。 当处理器的系统时钟保持有效时，通信总线可以访问卫星。 在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。

公开(公告)号：US06961875B2

公开(公告)日：2005-11-01

申请号：US09815548

申请日：2001-03-22

申请人： Michael Stephen Floyd ,  Balaram Sinharoy

发明人： Michael Stephen Floyd ,  Balaram Sinharoy

IPC分类号： G06F9/44 ,  G06F11/00 ,  G06F11/36

CPC分类号： G06F11/3636

摘要： A trace array having M entries with corresponding M addresses is used to store the states of input signals. The M addresses of the trace array are sequenced with a counter that counts a clock beginning at a starting count and counting to an ending count. If the ending count is exceeded, the counter starts over at the starting count. The counter outputs are decoded to addresses of the trace array. An event signal is generated on the occurrence of an operation of interest and the counter is started and stopped in response to sequences of the event signals, thus starting and stopping the recording of states of the input signals in the trace array. When an error or particular condition signal occurs, traces corresponding to the input signals are saved in the trace array. A start signal enables tracing and event logic generates event sequence signals which alternately start and stop the recording of traces. The event sequences are programmed by inputs to enable guaranteed statistical chances of capturing states of the input signals corresponding to a particular event signal occurring before an error or another event signal.

摘要翻译： 使用具有对应M地址的M个条目的跟踪数组来存储输入信号的状态。 跟踪数组的M地址用计数器计数，该计数器从起始计数开始计数一个时钟，并计数到结束计数。 如果超出结束计数，则计数器从起始计数开始。 计数器输出被解码为跟踪数组的地址。 在感兴趣的操作的发生时产生事件信号，并且响应于事件信号的序列开始和停止计数器，从而启动和停止跟踪阵列中的输入信号的状态的记录。 当发生错误或特定条件信号时，对应于输入信号的迹线将保存在跟踪数组中。 起始信号使跟踪和事件逻辑产生交替地启动和停止记录记录的事件序列信号。 事件序列由输入编程，以使保证的统计机会能够捕捉与在错误或其它事件信号之前发生的特定事件信号相对应的输入信号的状态。

公开(公告)号：US20080141000A1

公开(公告)日：2008-06-12

申请号：US12033385

申请日：2008-02-19

申请人： Michael Stephen Floyd ,  Larry Scott Leitner

发明人： Michael Stephen Floyd ,  Larry Scott Leitner

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。