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公开(公告)号：US07657772B2
公开(公告)日：2010-02-02
申请号：US10366437
申请日：2003-02-13
CPC分类号： H01L27/0248 , G01K7/425
摘要： An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.
摘要翻译： 一种具有温度敏感电路（TSC）的集成电路，用于产生指示TSC附近的衬底温度的信号。 集成电路具有被配置为从至少一个TSC接收TSC信号并且将TSC信号转换成指示集成电路的温度的信号的电路。 热控制电路将集成电路温度与阈值进行比较，并在温度超过阈值时产生校正动作信号。 校正动作信号被提供给校正动作电路，优选地被配置为修改IC的操作以降低接近相应TSC的IC温度。
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2.发明授权Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control 失效通过软件控制动态重新校准VLSI芯片热传感器的方法和装置公开(公告)号：US06879928B2
公开(公告)日：2005-04-12
申请号：US10346295
申请日：2003-01-16
申请人： Joachim Gerhard Clabes , Lawrence Joseph Powell, Jr. , Daniel Lawrence Stasiak , Michael Fan Wang , Balaram Sinharoy , Michael Stephen Floyd
发明人： Joachim Gerhard Clabes , Lawrence Joseph Powell, Jr. , Daniel Lawrence Stasiak , Michael Fan Wang , Balaram Sinharoy , Michael Stephen Floyd
IPC分类号： G01R31/28 , G01K3/00 , G01K7/32 , G01K11/22 , G01K15/00 , G06F19/00 , H01L21/822 , H01L27/04
摘要： The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.
摘要翻译： 本发明提供了用于校准阈值温度的集成电路VLSI温度系统。 温度敏感环形振荡器（TSRO）产生TSRO校准参数。 存储器可用于存储TSRO校准参数。 模块可用于从TSRO校准参数确定阈值TSRO振荡频率。 存储器可用于存储至少一个阈值TSRO振荡频率。
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公开(公告)号：US07051221B2
公开(公告)日：2006-05-23
申请号：US10425399
申请日：2003-04-28
IPC分类号： G06F1/32
CPC分类号： G06F9/3017 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/30149 , G06F9/3802 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D50/20
摘要： A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.
摘要翻译： 微处理器包括具有动态功率节省电路的功能块，功能块控制电路和热控制单元。 功能块控制电路能够在检测到过温度条件时自动改变其相关功能块的性能特性。 热控制单元接收指示处理器温度超过阈值的过温度信号，并响应于该信号调用一个或多个功能块控制单元。 功能块控制单元通过减少处理器活动，降低处理器性能或两者来响应来自热控制单元的信号。 导致动态省电电路参与的活动减少。 功能块控制单元可以通过多种方式来抑制性能，包括减少处理器内可利用的并行性，暂停无序执行，减少有效的资源大小等。
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公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译： 一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。 为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。 说明性实施例确定了处理器的目标功率效率模式。 一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。
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5.发明授权Synchronizing triggering of multiple hardware trace facilities using an existing system bus 失效使用现有系统总线同步触发多个硬件跟踪工具公开(公告)号：US07979750B2
公开(公告)日：2011-07-12
申请号：US12144422
申请日：2008-06-23
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.
摘要翻译： 在用于使用现有总线触发多个硬件跟踪设备的数据处理系统中公开了一种方法，装置和计算机程序产品。 多个硬件跟踪设备包括第一个硬件跟踪设备和第二个硬件跟踪设备。 数据处理系统包括第一处理器，其包括第一硬件跟踪设备和利用系统总线耦合在一起的第一处理单元，以及包括第二硬件跟踪设备的第二处理器和利用系统耦合在一起的第二处理单元 总线。 当处理器处于正常的非跟踪模式时，利用系统总线在第一和第二处理单元之间传送信息，其中信息根据标准系统总线协议被格式化。 触发事件使用相同的标准系统总线传输到硬件跟踪设备，触发事件也根据标准系统总线协议进行格式化。
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6.发明授权Method of seamlessly integrating thermal event information data with performance monitor data 有权将热事件信息数据与性能监视数据无缝集成的方法公开(公告)号：US07472315B2
公开(公告)日：2008-12-30
申请号：US11054292
申请日：2005-02-09
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。
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7.发明申请INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING 有权智能SMT螺纹连接检测进入帐户共享资源内容/阻塞公开(公告)号：US20080141000A1
公开(公告)日：2008-06-12
申请号：US12033385
申请日：2008-02-19
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/3842 , G06F9/3867 , G06F11/0715 , G06F11/0721 , G06F11/0757 , G06F11/1407
摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.
摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。
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公开(公告)号：US07305586B2
公开(公告)日：2007-12-04
申请号：US10424485
申请日：2003-04-25
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.
摘要翻译： 微处理器包括外部可访问端口和连接到端口的串行通信总线。 处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。 该卫星使外部代理可以通过串行总线直接向管线提供指令。 专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。 在执行指令期间，执行流水线可以访问专用寄存器。 以这种方式，卫星电路使外部代理能够访问架构状态。 当处理器的系统时钟保持有效时，通信总线可以访问卫星。 在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。
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9.发明授权Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components 有权动态，非侵入式检测热插拔问题组件，并从问题组件重新分配系统资源公开(公告)号：US07117388B2
公开(公告)日：2006-10-03
申请号：US10424278
申请日：2003-04-28
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/2028 , G06F11/2289
摘要： A method, system, and data processing system for dynamic detection of problem components in a hot-plug processing system and automatic removal of the problem component via hot-removal methods without disrupting processing of the overall system. A data processing system that provides a non-disruptive, hot-plug functionality is designed with a additional logic for initiating and/or completing a sequence of factory level tests on hot-pluggable components to determine if the component if functioning properly. When a component is not functioning properly, the OS re-allocates the workload of the component to other component so the system, and when the OS completes the re-allocation, the service element initiates the hot removal of the component so that the component is logically and electrically separated from the system.
摘要翻译： 一种用于动态检测热插拔处理系统中的问题组件的方法，系统和数据处理系统，并且通过热删除方法自动移除问题组件，而不会中断整个系统的处理。 提供无中断的热插拔功能的数据处理系统设计有一个额外的逻辑，用于启动和/或完成热插拔组件上的一系列工厂级测试，以确定组件是否正常工作。 当组件运行不正常时，操作系统将组件的工作负载重新分配给其他组件，以便系统，并且当操作系统完成重新分配时，服务组件启动组件的热删除，以使组件 与系统逻辑和电气分离。
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10.发明授权Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP 有权SMP中服务器节点的无中断，动态热插拔和热删除公开(公告)号：US06990545B2
公开(公告)日：2006-01-24
申请号：US10424277
申请日：2003-04-28
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： A data processing system that provides hot-plug add and remove functionality for individual, hot-pluggable components without disrupting current operations of the overall processing system. The processing system includes an interconnect fabric that includes hot plug connector at which an external hot-pluggable component can be coupled to the data processing system and logic components include configuration logic and routing and operating logic. When a hot-pluggable component is connected to the hot plug connector, the service element automatically detects the connection and selects the correct configuration file for the extended system. Once the configuration file is loaded and the system checks of the new element indicates the new element is ready for integration, the new element is integrated into the existing system, and the OS allocates workload to the new element. From a customer perspective, the entire process thus occurs without powering down or disrupting the operation of the existing element.
摘要翻译： 一种数据处理系统，可为单个热插拔组件提供热插拔添加和删除功能，而不会中断整个处理系统的当前操作。 处理系统包括互连结构，其包括热插拔连接器，外部可热插拔组件可以连接到数据处理系统，逻辑组件包括配置逻辑和路由和操作逻辑。 当热插拔组件连接到热插拔连接器时，服务元件会自动检测连接并为扩展系统选择正确的配置文件。 一旦加载了配置文件，并且新元素的系统检查指示新元素可以进行集成，则将新元素集成到现有系统中，并且操作系统将工作负载分配给新元素。 从客户的角度来看，整个过程都是在不掉电或破坏现有元素的操作的情况下进行的。
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