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公开(公告)号：US09153312B2
公开(公告)日：2015-10-06
申请号：US13975128
申请日：2013-08-23
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: G11C8/00 , G11C11/408 , H04L25/00 , G11C7/02 , G11C7/10
CPC classification number: G11C11/4085 , G11C7/02 , G11C7/1069 , G11C7/1096 , H04L25/00 , H04L25/03343 , H04L25/03885
Abstract: Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.
Abstract translation: 公开了用于发射机电路的方法和装置。 一个示例性装置包括预驱动器电路，其被配置为响应于接收的数据提供转换控制信号，以及主驱动器电路，被配置为响应于转换控制信号来驱动输出节点。 所述装置还包括反馈电路，其被配置为响应于所述输出节点的电压达到或超过预定阈值来提供反馈控制信号;以及均衡器驱动器电路，被配置为辅助所述主驱动器电路驱动所述输出节点， 至少一个预驱动电路和反馈电路。
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公开(公告)号：US11606229B2
公开(公告)日：2023-03-14
申请号：US17381987
申请日：2021-07-21
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis , Feng Lin
Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
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公开(公告)号：US11038724B2
公开(公告)日：2021-06-15
申请号：US16701020
申请日：2019-12-02
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.
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Patent Agency Ranking
公开(公告)号：US10530617B2
公开(公告)日：2020-01-07
申请号：US15885532
申请日：2018-01-31
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.
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公开(公告)号：US20190252356A1
公开(公告)日：2019-08-15
申请号：US16397038
申请日：2019-04-29
Applicant: Micron Technology, Inc.
Inventor： Feng Lin , Yuanzhong Wan
IPC: H01L25/065 , G11C11/4076 , G11C11/4091 , G11C7/10
CPC classification number: H01L25/0657 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4091 , H01L2225/06541 , H01L2225/06565
Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.
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公开(公告)号：US20150055431A1
公开(公告)日：2015-02-26
申请号：US13975128
申请日：2013-08-23
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03K3/01 , G11C11/408
CPC classification number: G11C11/4085 , G11C7/02 , G11C7/1069 , G11C7/1096 , H04L25/00 , H04L25/03343 , H04L25/03885
Abstract: Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.
Abstract translation: 公开了用于发射机电路的方法和装置。 一个示例性装置包括预驱动器电路，其被配置为响应于接收的数据提供转换控制信号，以及主驱动器电路，被配置为响应于转换控制信号来驱动输出节点。 所述装置还包括反馈电路，其被配置为响应于所述输出节点的电压达到或超过预定阈值来提供反馈控制信号;以及均衡器驱动器电路，被配置为辅助所述主驱动器电路驱动所述输出节点， 至少一个预驱动电路和反馈电路。
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公开(公告)号：US20140313844A1
公开(公告)日：2014-10-23
申请号：US13866712
申请日：2013-04-19
Applicant: MICRON TECHNOLOGY, INC
Inventor： Feng Lin
CPC classification number: H03K5/003 , G11C7/1057 , G11C7/1069 , G11C2207/107
Abstract: An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit. The pre-driver circuit can modify a data signal in response to the feedback control signal and the data signal. A driver circuit is coupled to the pre-driver circuit and can provide a driver output signal responsive to the modified data signal. A receiver can be coupled to the driver to receive the driver output signal. The receiver includes a level shifting circuit that shifts the received signal to a voltage level determined by a selected signaling interface.
Abstract translation: I / O收发器包括具有反馈电路的驱动器，该反馈电路具有模式选择信号输入，串行数据信号输入和驱动器输出信号输入。 反馈电路可以提供耦合到预驱动器电路的反馈控制信号。 预驱动器电路可以响应于反馈控制信号和数据信号来修改数据信号。 驱动器电路耦合到预驱动器电路，并且可以响应于修改的数据信号来提供驱动器输出信号。 接收器可以耦合到驱动器以接收驱动器输出信号。 接收机包括电平移位电路，该电平移位电路将接收到的信号转换到由所选信令接口确定的电压电平。
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公开(公告)号：US20130314140A1
公开(公告)日：2013-11-28
申请号：US13953500
申请日：2013-07-29
Applicant: Micron Technology, Inc.
Inventor： Feng Lin
IPC: H03H11/26
CPC classification number: H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.
Abstract translation: 描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。 描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。 偏置信号可以部分地基于模拟延迟线的操作频率。
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