公开(公告)号：US20220171548A1

公开(公告)日：2022-06-02

申请号：US17110197

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：US11342007B2

公开(公告)日：2022-05-24

申请号：US16989555

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh

IPC: G11C16/04 ,  G11C5/14 ,  H01L23/64 ,  G11C5/06

Abstract: Methods, systems, and devices for capacitance allocation based on system impedance are described. A memory device may include a first voltage rail for distributing a first supply voltage to an array of memory cells. The memory device may be coupled with a circuit using a pad of the memory device; that is, the memory device may be coupled with other circuitry within a package or board. The memory device may determine an impedance associated with the circuit, and may couple one or more capacitors with the first voltage rail based on the impedance. The memory device may include a second voltage rail for distributing a second supply voltage to the array of memory cells. The memory device may compare the performance of the first and second voltage rails and couple one or more capacitors with the first voltage rail or the second voltage rail based on the comparison.

公开(公告)号：US10796729B2

公开(公告)日：2020-10-06

申请号：US16268092

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/22 ,  G11C5/06 ,  G11C11/4091 ,  G06F13/16 ,  G11C11/56 ,  G11C11/408

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US20200310520A1

公开(公告)日：2020-10-01

申请号：US16369804

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

公开(公告)号：US20190081024A1

公开(公告)日：2019-03-14

申请号：US16190523

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

公开(公告)号：US11967359B2

公开(公告)日：2024-04-23

申请号：US18120136

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H02M3/158 ,  H03F3/45

CPC classification number: G11C11/4076 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C11/4074 ,  H02M3/158 ,  H03F3/45071

Abstract: Methods, systems, and devices for varying a time average for feedback of a memory system are described. An apparatus may include a voltage supply, a memory array, and a regulator coupled with the voltage supply and memory array and configured to supply a first voltage received from the voltage supply to the memory array. The apparatus may also include a voltage sensor configured to measure a second voltage of the memory array and a digital feedback circuit coupled with the memory array and regulator and configured to generate feedback comprising information averaged over a duration based at least in part on the second voltage measured by the voltage sensor and to transmit an analog signal to the regulator based at least in part on the feedback.

公开(公告)号：US11763874B2

公开(公告)日：2023-09-19

申请号：US17480685

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/00 ,  G11C11/4074 ,  G06F3/06

CPC classification number: G11C11/4074 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US20230118893A1

公开(公告)日：2023-04-20

申请号：US18084149

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F1/3225

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：US11574687B2

公开(公告)日：2023-02-07

申请号：US17514858

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Fuad Badrieh ,  Thomas H. Kinsley

IPC: G11C5/14 ,  G11C16/30 ,  G06F1/28 ,  G06F1/3296

Abstract: A memory device may include a pin for receiving a direct current (DC) voltage indicating an operating configuration setting of the memory device and for communicating an alternating current (AC) voltage signal that provides feedback to a power management component. The memory device may determine that a supply voltage is outside of a target range, and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled with a capacitive component the passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

公开(公告)号：US20220358988A1

公开(公告)日：2022-11-10

申请号：US17315711

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C11/4074 ,  G11C11/22

Abstract: Methods, systems, and devices for voltage adjustment of memory dies based on weighted feedback are described. A supply voltage may be measured at various areas of a memory die, weights may be applied to the measured voltages based on the area from which the particular voltage was measured. The supply voltage may be adjusted based on the weighted signals. The signals may be weighted using digital or analog techniques. Different durations of time in which oscillations from an oscillator circuit are counted may provide weighting for a signal. Weights applied to the signals may be dynamically adjusted, which may allow the weights to be tuned or changed based on changes to operating conditions of the memory dies.