公开(公告)号：US20190121560A1

公开(公告)日：2019-04-25

申请号：US15981708

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  James Brian Johnson

IPC: G06F3/06 ,  H01L25/065 ,  H01L23/538 ,  H01L25/18 ,  G11C11/4076 ,  H01L23/14 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/22 ,  G06F11/10

Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

公开(公告)号：US20240237363A1

公开(公告)日：2024-07-11

申请号：US18400994

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Ameen D. Akel ,  Kunal R. Parekh ,  Amy Rae Griffin ,  Eiichi Nakano

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.

公开(公告)号：US11837318B2

公开(公告)日：2023-12-05

申请号：US17843244

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson

IPC: G11C7/10 ,  G06F1/10 ,  G06F1/12 ,  G11C7/22

CPC classification number: G11C7/1072 ,  G06F1/10 ,  G06F1/12 ,  G11C7/1006 ,  G11C7/222

Abstract: Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.

公开(公告)号：US20140204685A1

公开(公告)日：2014-07-24

申请号：US14223079

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/22

Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.

Abstract translation: 本发明的实施例描述了将数据驱动到总线上。 这些实施例包括具有耦合到总线的数据捕获电路的数据驱动器电路。 数据采集​​电路相对于写入选通信号接收数据，并响应写入选通信号的第一个边缘并且响应于写入选通信号的第二个边缘的至少一个第二数位捕获数据的第一个数字。 数据驱动器电路包括反馈捕获电路，其以与数据捕获电路基本相同的方式捕获每个数字，并且产生指示何时锁存每个数字的锁存控制信号。 锁存控制信号被提供给写入控制电路，该写入控制电路确定哪个数字相对于定时首先被锁存，并且产生一个选择控制信号，以便按照接收数字的顺序将捕获的数字驱动到总线上。