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    INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
    1.
    发明申请
    INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20240403165A1

    公开(公告)日：2024-12-05

    申请号：US18667799

    申请日：2024-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Nathan A. Eckel ,  James Brian Johnson ,  Paul A. Laberge

    IPC: G06F11/10 ,  G06F11/14

    Abstract: Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

    CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES
    3.
    发明申请
    CLOCK LOCKING FOR PACKET BASED COMMUNICATIONS OF MEMORY DEVICES 有权

    公开(公告)号：US20220374039A1

    公开(公告)日：2022-11-24

    申请号：US17843244

    申请日：2022-06-17

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson

    IPC: G06F1/12 ,  G11C7/22

    Abstract: Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.

    FRAME PROTOCOL OF MEMORY DEVICE
    4.
    发明申请
    FRAME PROTOCOL OF MEMORY DEVICE 有权

    公开(公告)号：US20220121609A1

    公开(公告)日：2022-04-21

    申请号：US17562550

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth

    IPC: G06F13/42 ,  G06F15/167

    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

    LATENCY OFFSET FOR FRAME-BASED COMMUNICATIONS
    5.
    发明申请
    LATENCY OFFSET FOR FRAME-BASED COMMUNICATIONS 有权

    公开(公告)号：US20210191622A1

    公开(公告)日：2021-06-24

    申请号：US16951299

    申请日：2020-11-18

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

    FRAME PROTOCOL OF MEMORY DEVICE
    6.
    发明申请
    FRAME PROTOCOL OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20200159687A1

    公开(公告)日：2020-05-21

    申请号：US16773784

    申请日：2020-01-27

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth

    IPC: G06F13/42 ,  G06F15/167

    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

    DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS
    8.
    发明公开
    DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS 审中-公开

    公开(公告)号：US20240355371A1

    公开(公告)日：2024-10-24

    申请号：US18607033

    申请日：2024-03-15

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

    IPC: G11C7/10 ,  G11C7/22 ,  G11C29/52

    CPC classification number: G11C7/1069 ,  G11C7/222 ,  G11C29/52

    Abstract: Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

    MEMORY WITH PARALLEL MAIN AND TEST INTERFACES
    10.
    发明公开
    MEMORY WITH PARALLEL MAIN AND TEST INTERFACES 审中-公开

    公开(公告)号：US20240071556A1

    公开(公告)日：2024-02-29

    申请号：US17821676

    申请日：2022-08-23

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

    IPC: G11C29/56 ,  G11C7/10

    CPC classification number: G11C29/56004 ,  G11C7/1039 ,  G11C29/56016 ,  G11C2029/5602

    Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

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