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    Shared parity protection
    31.
    发明授权
    Shared parity protection 有权

    公开(公告)号：US10970170B2

    公开(公告)日：2021-04-06

    申请号：US16555014

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan Scott Parry ,  Giuseppe Cariello

    IPC: G06F11/10 ,  G06F3/06

    Abstract: A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.

    AUTOMATED POWER DOWN BASED ON STATE OF FIRMWARE
    33.
    发明申请
    AUTOMATED POWER DOWN BASED ON STATE OF FIRMWARE 有权

    公开(公告)号：US20210011796A1

    公开(公告)日：2021-01-14

    申请号：US17036973

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Jonathan Scott Parry ,  Nadav Grosz

    IPC: G06F11/07 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237

    Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

    Dynamic memory address write policy translation based on performance needs
    34.
    发明授权
    Dynamic memory address write policy translation based on performance needs 有权

    公开(公告)号：US12248705B2

    公开(公告)日：2025-03-11

    申请号：US17865760

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Jonathan Scott Parry

    IPC: G06F3/06 ,  G06F12/06

    Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

    Increased efficiency obfuscated logical-to-physical map management
    36.
    发明授权
    Increased efficiency obfuscated logical-to-physical map management 有权

    公开(公告)号：US11556481B2

    公开(公告)日：2023-01-17

    申请号：US16554937

    申请日：2019-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Nadav Grosz ,  Jonathan Scott Parry

    IPC: G06F12/14 ,  G06F12/02

    Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

    Peak power management in a memory device
    37.
    发明授权
    Peak power management in a memory device 有权

    公开(公告)号：US11520497B2

    公开(公告)日：2022-12-06

    申请号：US17110103

    申请日：2020-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    39.
    发明申请
    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES 有权

    公开(公告)号：US20220214821A1

    公开(公告)日：2022-07-07

    申请号：US17702217

    申请日：2022-03-23

    Applicant: Micron Technology, Inc.

    Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Chistian M. Gyllenskog ,  Kulachet Tanpairoj

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

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