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公开(公告)号：US11488681B2
公开(公告)日：2022-11-01
申请号：US17170386
申请日：2021-02-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Dallabora , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.
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公开(公告)号：US11456033B2
公开(公告)日：2022-09-27
申请号：US16846481
申请日：2020-04-13
Applicant: Micron Technology, Inc.
Inventor： Daniele Balluchi , Paolo Amato , Graziano Mirichigni , Danilo Caraccio , Marco Sforzin , Marco Dallabora
Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.
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公开(公告)号：US11327892B2
公开(公告)日：2022-05-10
申请号：US16893982
申请日：2020-06-05
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F12/0862 , G06F12/10 , G06F3/06
Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
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公开(公告)号：US11209986B2
公开(公告)日：2021-12-28
申请号：US16541571
申请日：2019-08-15
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F11/10 , G06F12/1009 , G11C16/34 , G06F3/06
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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公开(公告)号：US20210208988A1
公开(公告)日：2021-07-08
申请号：US17206881
申请日：2021-03-19
Applicant: Micron Technology, Inc.
Inventor： Marco Dallabora , Emanuele Confalonieri , Paolo Amato , Daniele Balluchi , Danilo Caraccio
Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.
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Patent Agency Ranking
公开(公告)号：US20210191887A1
公开(公告)日：2021-06-24
申请号：US17192602
申请日：2021-03-04
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Marco Dallabora , Daniele Balluchi , Paolo Amato , Luca Porzio
Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.
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公开(公告)号：US10943659B2
公开(公告)日：2021-03-09
申请号：US16744643
申请日：2020-01-16
Applicant: Micron Technology, Inc.
Inventor： Marco Dallabora , Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.
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公开(公告)号：US10649665B2
公开(公告)日：2020-05-12
申请号：US15345919
申请日：2016-11-08
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Marco Dallabora , Paolo Amato , Danilo Caraccio , Daniele Balluchi
Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.
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公开(公告)号：US20200082900A1
公开(公告)日：2020-03-12
申请号：US16128113
申请日：2018-09-11
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Dallabora , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri
Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.
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公开(公告)号：US20190122709A1
公开(公告)日：2019-04-25
申请号：US16215693
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli , Marco Dallabora
IPC: G11C7/10
CPC classification number: G11C7/1096 , G11C13/00 , G11C13/0061 , G11C13/0069 , G11C2013/0076 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/79
Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.
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