公开(公告)号：US10922262B2

公开(公告)日：2021-02-16

申请号：US16840281

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G11C7/00 ,  G06F13/42 ,  G11C11/4093 ,  G11C11/402 ,  H01L27/108

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US20200233828A1

公开(公告)日：2020-07-23

申请号：US16840281

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Yuki Ebihara ,  Seiji Narui

IPC: G06F13/42 ,  G11C11/4093 ,  H01L27/108 ,  G11C11/402

Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

公开(公告)号：US20190122708A1

公开(公告)日：2019-04-25

申请号：US16225303

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/10 ,  G11C7/22 ,  G11C19/28

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US20180341575A1

公开(公告)日：2018-11-29

申请号：US15606956

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G06F12/02 ,  H01L23/522

CPC classification number: G06F12/02 ,  G06F2212/1016 ,  G06F2212/1028 ,  H01L23/5226

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US20150213860A1

公开(公告)日：2015-07-30

申请号：US14607858

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Chikara Kondo

IPC: G11C7/22 ,  H01L25/065 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06

CPC classification number: G11C7/22 ,  G11C5/02 ,  G11C5/063 ,  G11C7/10 ,  G11C11/4097 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.

Abstract translation: 本公开中公开的半导体器件包括形成在半导体衬底的第一表面上的第一端子，形成在与第一表面相对的半导体衬底的第二表面上方的第二端子，穿过半导体的第一贯穿衬底通孔（TSV） 基板和先进先出（FIFO）电路，其中第一TSV和FIFO电路串联耦合在第一端子和第二端子之间。