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公开(公告)号：US20220382487A1
公开(公告)日：2022-12-01
申请号：US17771668
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Xinghui Duan , Massimo Zucchinali
Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).
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公开(公告)号：US11341041B2
公开(公告)日：2022-05-24
申请号：US16940015
申请日：2020-07-27
Applicant: Micron Technology, Inc.
Inventor： Zhao Cui , Eric Kwok Fung Yuen , Guan Zhong Wang , Xinghui Duan , Giuseppe D'Eliseo , Giuseppe Ferrari
IPC: G06F12/02 , G06F12/0873
Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.
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Patent Agency Ranking
公开(公告)号：US20220066926A1
公开(公告)日：2022-03-03
申请号：US17521340
申请日：2021-11-08
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
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公开(公告)号：US11132136B2
公开(公告)日：2021-09-28
申请号：US16077175
申请日：2017-12-13
Applicant: Micron Technology, Inc.
Inventor： Zhao Cui , Eric Kwok Fung Yuen , Guan Zhong Wang , Xinghui Duan , Hua Chen Li
Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.
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公开(公告)号：US20210279010A1
公开(公告)日：2021-09-09
申请号：US17331357
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US20200226059A1
公开(公告)日：2020-07-16
申请号：US16742215
申请日：2020-01-14
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
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公开(公告)号：US20200004673A1
公开(公告)日：2020-01-02
申请号：US16024380
申请日：2018-06-29
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
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