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    COUNTER OPERATION IN A STATE MACHINE LATTICE
    32.
    发明申请
    COUNTER OPERATION IN A STATE MACHINE LATTICE 有权
    状态机计数器中的计数器运行

    公开(公告)号：US20150253755A1

    公开(公告)日：2015-09-10

    申请号：US14722941

    申请日：2015-05-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G05B19/045 ,  H03K19/177

    CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不多于）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。

    COUNTER OPERATION IN A STATE MACHINE LATTICE
    33.
    发明申请
    COUNTER OPERATION IN A STATE MACHINE LATTICE 有权
    状态机计数器中的计数器运行

    公开(公告)号：US20140115299A1

    公开(公告)日：2014-04-24

    申请号：US14143398

    申请日：2013-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G06F15/82

    CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不超过）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。

    System and method for individual addressing
    35.
    发明授权
    System and method for individual addressing 有权

    公开(公告)号：US10521366B2

    公开(公告)日：2019-12-31

    申请号：US16400739

    申请日：2019-05-01

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F12/10 ,  G06F13/12 ,  G06F13/40 ,  G06F13/28

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    36.
    发明申请
    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开

    公开(公告)号：US20190258592A1

    公开(公告)日：2019-08-22

    申请号：US16400739

    申请日：2019-05-01

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    System and method for individual addressing
    37.
    发明授权
    System and method for individual addressing 有权

    公开(公告)号：US10339071B2

    公开(公告)日：2019-07-02

    申请号：US16192509

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

    IPC: G06F12/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    VALIDATION OF A SYMBOL RESPONSE MEMORY
    38.
    发明申请
    VALIDATION OF A SYMBOL RESPONSE MEMORY 审中-公开

    公开(公告)号：US20180322006A1

    公开(公告)日：2018-11-08

    申请号：US16030479

    申请日：2018-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G06F11/10 ,  H03M13/09

    CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

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