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    SPACE EFFICIENT RANDOM DECISION FOREST MODELS IMPLEMENTATION UTILIZING AUTOMATA PROCESSORS
    1.
    发明公开
    SPACE EFFICIENT RANDOM DECISION FOREST MODELS IMPLEMENTATION UTILIZING AUTOMATA PROCESSORS 审中-公开

    公开(公告)号：US20240185139A1

    公开(公告)日：2024-06-06

    申请号：US18439024

    申请日：2024-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Yao Fu ,  Paul Glendenning ,  Tommy Tracy, II ,  Eric Jonas

    IPC: G06N20/20 ,  G06N5/01 ,  G06N20/00

    CPC classification number: G06N20/20 ,  G06N5/01 ,  G06N20/00

    Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and to receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.

    Validation of a symbol response memory
    4.
    发明授权
    Validation of a symbol response memory 有权

    公开(公告)号：US10402265B2

    公开(公告)日：2019-09-03

    申请号：US16030479

    申请日：2018-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

    IPC: G11C29/00 ,  G06F11/10 ,  H03M13/09

    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    5.
    发明申请
    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开

    公开(公告)号：US20190087360A1

    公开(公告)日：2019-03-21

    申请号：US16192509

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B. Noyes

    IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

    CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    Boolean logic in a state machine lattice
    9.
    发明授权
    Boolean logic in a state machine lattice 有权
    状态机格子中的布尔逻辑

    公开(公告)号：US09118327B2

    公开(公告)日：2015-08-25

    申请号：US14087973

    申请日：2013-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: G05B19/045 ,  G06F7/00 ,  G06F3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F17/50

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
    10.
    发明申请
    METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE 有权
    用于在状态机中路由的方法和系统

    公开(公告)号：US20140204956A1

    公开(公告)日：2014-07-24

    申请号：US14223507

    申请日：2014-03-24

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

    IPC: G06K9/00 ,  H04L12/883

    CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

    Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

    Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。

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