公开(公告)号：US10998031B2

公开(公告)日：2021-05-04

申请号：US16569588

申请日：2019-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C7/02 ,  G11C11/22 ,  H01L27/11507 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509 ,  G11C11/56

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US10998027B2

公开(公告)日：2021-05-04

申请号：US16035147

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  G11C5/02

Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.

公开(公告)号：US20210074357A1

公开(公告)日：2021-03-11

申请号：US16953092

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael A. Shore

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/4091 ,  H01L27/11507 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/00 ,  H01L27/11509 ,  H01L27/105

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

公开(公告)号：US10916548B1

公开(公告)日：2021-02-09

申请号：US16522336

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  G11C11/404 ,  G11C11/4097 ,  H01L29/786 ,  H01L27/02 ,  H01L23/528 ,  G11C11/4091

Abstract: An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.

公开(公告)号：US10896717B2

公开(公告)日：2021-01-19

申请号：US16235163

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C5/14 ,  G11C11/4074 ,  G06F3/06

Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.

公开(公告)号：US10783948B2

公开(公告)日：2020-09-22

申请号：US16425769

申请日：2019-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11502

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US10748596B2

公开(公告)日：2020-08-18

申请号：US16544587

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20200051982A1

公开(公告)日：2020-02-13

申请号：US16514693

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/4094

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20200051614A1

公开(公告)日：2020-02-13

申请号：US16408095

申请日：2019-05-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4091 ,  G11C11/408

Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US10468421B2

公开(公告)日：2019-11-05

申请号：US16204409

申请日：2018-11-29

Applicant: Micron Technology Inc.

Inventor： Debra M. Bell ,  Scott J. Derner

IPC: G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  G11C11/419

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.