Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory

    公开(公告)号:US10998031B2

    公开(公告)日:2021-05-04

    申请号:US16569588

    申请日:2019-09-12

    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

    Pseudo-non-volatile memory cells
    2.
    发明授权

    公开(公告)号:US10896717B2

    公开(公告)日:2021-01-19

    申请号:US16235163

    申请日:2018-12-28

    Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.

    Pre-sense gut node amplification in sense amplifier

    公开(公告)号:US11967362B2

    公开(公告)日:2024-04-23

    申请号:US17829737

    申请日:2022-06-01

    CPC classification number: G11C11/4091

    Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

    Pre-Sense Gut Node Amplification in Sense Amplifier

    公开(公告)号:US20230395130A1

    公开(公告)日:2023-12-07

    申请号:US17829737

    申请日:2022-06-01

    CPC classification number: G11C11/4091

    Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

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