公开(公告)号：US08476630B2

公开(公告)日：2013-07-02

申请号：US13314327

申请日：2011-12-08

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L29/04

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.

Abstract translation: 导电油墨的图案设置在晶片的未镶嵌集成电路的顶侧上，并且通常在晶片探测之后，去除导电油墨的图案。 导电油墨图案在集成电路上的接合焊盘和设置在集成电路的顶侧上的大接触焊盘之间提供电路径。 每个大的接触焊盘的面积比对应的接合焊盘大得多，并且间隔开，使得大接触焊盘的间距远大于接合焊盘的间距。 在本发明的一个方面，导电油墨包括导电颗粒和晶片接合热固性塑料的混合物。 在本发明的另一方面，导电油墨通过喷墨打印系统被加热并设置在晶片上。

公开(公告)号：US20120156811A1

公开(公告)日：2012-06-21

申请号：US13314327

申请日：2011-12-08

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.

Abstract translation: 导电油墨的图案设置在晶片的未镶嵌集成电路的顶侧上，并且通常在晶片探测之后，去除导电油墨的图案。 导电油墨图案在集成电路上的接合焊盘和设置在集成电路的顶侧上的大接触焊盘之间提供电路径。 每个大的接触焊盘的面积比对应的接合焊盘大得多，并且间隔开，使得大接触焊盘的间距远大于接合焊盘的间距。 在本发明的一个方面，导电油墨包括导电颗粒和晶片接合热固性塑料的混合物。 在本发明的另一方面，导电油墨通过喷墨打印系统被加热并设置在晶片上。

公开(公告)号：US20120149134A1

公开(公告)日：2012-06-14

申请号：US13292037

申请日：2011-11-08

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/66

CPC classification number: G01R31/2889 ,  G01R1/07307 ,  G01R31/2601 ,  H01L21/67 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6838 ,  H01L21/76256 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/014

Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.

Abstract translation: 晶片转换器设置有晶片接合热固性塑料的图案化层，并且可拆卸地与晶片连接，以便形成晶片/晶片转换器对。 晶片转换器在薄化工艺期间以及在晶片切割操作期间用作机械支撑。 然后将单片化的集成电路从晶片转换器移除。 在一些实施例中，在晶片减薄处理之后但在晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。 在其他实施例中，在晶片切割操作之后，但是在切割的晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。

公开(公告)号：US08088634B2

公开(公告)日：2012-01-03

申请号：US12617705

申请日：2009-11-12

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/26

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system.

Abstract translation: 导电油墨的图案设置在晶片的未镶嵌集成电路的顶侧上，并且通常在晶片探测之后，去除导电油墨的图案。 导电油墨图案在集成电路上的接合焊盘和设置在集成电路的顶侧上的大接触焊盘之间提供电路径。 每个大的接触焊盘的面积比对应的接合焊盘大得多，并且间隔开，使得大接触焊盘的间距远大于接合焊盘的间距。 在本发明的一个方面，导电油墨包括导电颗粒和晶片接合热固性塑料的混合物。 在本发明的另一方面，导电油墨通过喷墨打印系统被加热并设置在晶片上。

公开(公告)号：US07960986B2

公开(公告)日：2011-06-14

申请号：US12275226

申请日：2008-11-21

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

Abstract translation: 通过使晶片和边缘延伸的晶片转换器进入附接状态来提供对晶片的集成电路的访问以同时执行两种或更多种类型的测试。 边缘延伸晶片转换器具有设置在其上的晶片侧接触端子和询问侧接触端子，第一组晶片侧接触端子电耦合到第一组查询侧接触端子，以及第二组晶片 侧接触端子电耦合到第二组询问侧接触端子。 边缘延伸晶片转换器具有与附接的晶片大致共同延伸的中心部分，以及延伸超出通常由晶片的外圆周边缘限定的边界的边缘延伸部分。 至少一个集成电路的第一组焊盘电耦合到第一组晶片侧接触端子，并且集成电路的第二组焊盘电耦合到第二组晶片侧接触端子。 边缘延伸晶片转换器可以被成形为使得其边缘延伸部分不与其中心部分共面。

公开(公告)号：US07791174B2

公开(公告)日：2010-09-07

申请号：US12077670

申请日：2008-03-20

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L29/40

CPC classification number: H01L23/481 ,  G01R1/07342 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49139 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Apparatus and methods are provided for wafer translators having a silicon core, an isolating conductive ground plane, and copper and subjacent resin layers disposed on the ground plane. A silicon substrate having at least one major surface coated with an electrically conductive layer is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical drilling of via openings in a dielectric material; plating of copper, nickel, and gold layers; laser removal of metal; and chemical removal of metal; in order to produce a wafer translator having a silicon core. In further aspects of the present invention, alignment marks are formed and contact structures, such as stud bumps, are placed relative to a local set of alignment marks.

Abstract translation: 提供了用于具有硅芯，隔离导电接地平面以及设置在接地平面上的铜和相邻树脂层的晶片转换器的装置和方法。 具有涂覆有导电层的至少一个主表面的硅衬底经受许多印刷电路板制造操作，包括但不限于施加树脂涂覆的铜箔; 铜层机械研磨; 电介质材料中通孔的机械钻孔; 电镀铜，镍和金层; 激光去除金属; 并化学除去金属; 以产生具有硅芯的晶片转换器。 在本发明的另外的方面，形成对准标记，并且相对于本地对准标记集合放置诸如柱形凸起的接触结构。

公开(公告)号：US07724018B2

公开(公告)日：2010-05-25

申请号：US12365895

申请日：2009-02-04

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R27/28

CPC classification number: G01R31/286

Abstract: A translated wafer stand-in tester, being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The translated wafer stand-in tester may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract translation: 一种翻译的晶片待机测试仪，其是能够模拟被测翻译的晶片的形状因子和一些或所有行为的混合设备，其可操作以直接或远程地存储，量化，编码和传送来自 测试系统，包括但不限于焊盘压力，电接触和温度。 翻译的晶片待机测试器可以包括几个堆叠和附接的层，至少一个内层，包括可操作以与测试系统相互作用的电子组件。

公开(公告)号：US20100001750A1

公开(公告)日：2010-01-07

申请号：US12347995

申请日：2008-12-31

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  H05K1/00

CPC classification number: H01R12/79 ,  G01R31/2886

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract translation: 一种用于在一个或多个未设计的集成电路和集成电路外部的一个或多个测试电路之间提供电路径的装置包括具有第一主表面和第二主表面的柔性衬底，多个第一接触结构，其设置在中心 柔性基板的第一表面的一部分，设置在柔性基板的第一表面的周边环形区域中的多个第二接触结构，以及多个第一导电通路，多个第一导电通路中的每一个耦接 到相应的第一和第二接触结构，其中第二表面没有第一接触结构，第二接触结构和第一导电通路。

公开(公告)号：US20090189627A1

公开(公告)日：2009-07-30

申请号：US12325269

申请日：2008-12-01

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R1/07342 ,  G01R31/2886

Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Abstract translation: 通过边缘扩展晶片转换器提供对晶片上的集成电路的焊盘的并发电接口，其将信号从一个或多个集成电路上的一个或多个焊盘传送到边缘扩展晶片转换器的查询侧的接触端子 包括当晶片和边缘延伸晶片转换器处于可移除地附接状态时位于晶片上方的询问侧的部分以及位于由晶片和边缘延伸晶片转换器的相交处限定的区域之外的查询侧的部分 边缘延伸晶片转换器。 在本发明的另一方面，在位于边缘延伸晶片转换器的晶片侧的第二查询区域中的接触端子附加地提供对晶片上的集成电路焊盘的访问，该区域由其边界 外圆周和圆周。

公开(公告)号：US07489148B2

公开(公告)日：2009-02-10

申请号：US11881574

申请日：2007-07-27

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: H01R12/79 ,  G01R31/2886

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract translation: 一种用于在一个或多个未设计的集成电路和集成电路外部的一个或多个测试电路之间提供电路径的装置包括具有第一主表面和第二主表面的柔性衬底，多个第一接触结构，其设置在中心 柔性基板的第一表面的一部分，设置在柔性基板的第一表面的周边环形区域中的多个第二接触结构，以及多个第一导电通路，多个第一导电通路中的每一个耦接 到相应的第一和第二接触结构，其中第二表面没有第一接触结构，第二接触结构和第一导电通路。